STM32 Timers support generic 3 cells PWM to encode PWM number, period and
polarity.

Fixes: 61fc211c ("ARM: dts: stm32: add timers support to stm32mp157c")
Signed-off-by: NFabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: NAlexandre Torgue <alexandre.torgue@st.com>

Fix compilations warnings detected by -Wall W=1 compilation option:
- node has a unit name, but no reg property
Signed-off-by: NErwan Le Ray <erwan.leray@st.com>
Signed-off-by: NAlexandre Torgue <alexandre.torgue@st.com>

Booster for ADC analog input switches can be used when Vdda is below 2.7V
to get maximum ADC analog performances.
Add booster for ADC analog switches on stm32mp157c.
Signed-off-by: NFabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: NAlexandre Torgue <alexandre.torgue@st.com>

Enable m4 coprocessor for STM32MP157a-dk1 board.
Signed-off-by: NFabien Dessenne <fabien.dessenne@st.com>
Signed-off-by: NAlexandre Torgue <alexandre.torgue@st.com>

Declare reserved memories shared by the processors for STM32MP157a-dk1
Signed-off-by: NFabien Dessenne <fabien.dessenne@st.com>
Signed-off-by: NAlexandre Torgue <alexandre.torgue@st.com>

Enable m4 coprocessor for STM32MP157c-ed1 board.
Signed-off-by: NFabien Dessenne <fabien.dessenne@st.com>
Signed-off-by: NAlexandre Torgue <alexandre.torgue@st.com>

Declare reserved memories shared by the processors for STM32MP157c-ed1
board.
Signed-off-by: NFabien Dessenne <fabien.dessenne@st.com>
Signed-off-by: NAlexandre Torgue <alexandre.torgue@st.com>

Declare the M4 remote processor in a sub-node of the mlahb simple bus.
Signed-off-by: NFabien Dessenne <fabien.dessenne@st.com>
Signed-off-by: NAlexandre Torgue <alexandre.torgue@st.com>

Add missing vdda-supply required by STM32 ADC.

Fixes: 090992a9 ("ARM: dts: stm32: enable ADC on stm32h743i-eval
board")
Signed-off-by: NFabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: NAlexandre Torgue <alexandre.torgue@st.com>

Add missing vdda-supply required by STM32 ADC.

Fixes: 7465d811 ("ARM: dts: stm32: enable ADC on stm32f429i-eval
board")
Signed-off-by: NFabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: NAlexandre Torgue <alexandre.torgue@st.com>

vref fixed regulator shouldn't have unit address and reg properties.
Rename the label and phandle to "vref" according to the schematics.
Also remove it from simple-bus.

Fixes: 7465d811 ("ARM: dts: stm32: enable ADC on stm32f429i-eval
board")
Signed-off-by: NFabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: NAlexandre Torgue <alexandre.torgue@st.com>

This patch enables FMC2 NAND controller used on stm32mp157c-ev1.
Signed-off-by: NChristophe Kerello <christophe.kerello@st.com>
Signed-off-by: NAlexandre Torgue <alexandre.torgue@st.com>

This patch adds FMC2 NAND controller pins muxing used on stm32mp157c-ev1.
Signed-off-by: NChristophe Kerello <christophe.kerello@st.com>
Signed-off-by: NAlexandre Torgue <alexandre.torgue@st.com>

This patch adds FMC2 NAND controller support used by stm32mp157c SOC.
Signed-off-by: NChristophe Kerello <christophe.kerello@st.com>
Signed-off-by: NAlexandre Torgue <alexandre.torgue@st.com>

This patch activates dma for qspi on stm32mp157.
Signed-off-by: NLudovic Barre <ludovic.barre@st.com>
Signed-off-by: NAlexandre Torgue <alexandre.torgue@st.com>

The SPI to the display on the DIR-685 is active low, we were
just saved by the SPI library enforcing active low on everything
before, so set it as active low to avoid ambiguity.

Link: https://lore.kernel.org/r/20190715202101.16060-1-linus.walleij@linaro.org
Cc: stable@vger.kernel.org
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

The datasheet of S2MPS11 PMIC is slightly non-consistent in buck[78]
voltage regulators values.

1. The voltage tables for configuring their registers mention range of
   voltages: 0.750 V to 3.55 V,
2. The constrains in electrical specifications say output voltage range
   to be different (buck7: 1.2 V to 1.5 V, buck8: 1.8 V to 2.1 V).

Adjust the ranges to match the electrical specifications to stay on the
safe side.  Anyway these regulators stay at default value so this should
not have effect.
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>

The datasheet of S2MPS11 PMIC is slightly non-consistent in buck[78]
voltage regulators values.

1. The voltage tables for configuring their registers mention range of
   voltages: 0.750 V to 3.55 V,
2. The constrains in electrical specifications say output voltage range
   to be different (buck7: 1.2 V to 1.5 V, buck8: 1.8 V to 2.1 V).

Adjust the ranges to match the electrical specifications to stay on the
safe side.  Also change the name of regulators to match reality.  Anyway
these regulators stay at default value so this should not have effect.
Reported-by: NAnand Moon <linux.amoon@gmail.com>
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>

Mali400 GPU hardware module is a standard hardware module integrated to
Exynos3210/4210/4412 SoCs, so it should reside under the "/soc" node.
The only SoC components which are placed in the DT root, are those, which
are a part of CPUs: like ARM architected timers and ARM performance
measurement units.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>

The PMU module of Mali400 GPU is optional and it looks that it is not
present on Exynos4210, because any access to its registers causes external
abort. This patch removes "pmu" interrupt for Exynos4210 SoCs, so the
driver will skip the PMU module. This fixes following fault during kernel
boot:

    Unhandled fault: imprecise external abort (0x1406) at 0x00000000
    (lima_pmu_init) from [<c059e6f8>] (lima_device_init+0x244/0x5a0)
    (lima_device_init) from [<c059e40c>] (lima_pdev_probe+0x7c/0xd8)
    (lima_pdev_probe) from [<c05afcb8>] (platform_drv_probe+0x48/0x9c)
    (platform_drv_probe) from [<c05ad594>] (really_probe+0x1c4/0x400)
    (really_probe) from [<c05ad988>] (driver_probe_device+0x78/0x1b8)
    (driver_probe_device) from [<c05add30>] (device_driver_attach+0x58/0x60)
    (device_driver_attach) from [<c05ade34>] (__driver_attach+0xfc/0x160)
    (__driver_attach) from [<c05ab650>] (bus_for_each_dev+0x68/0xb4)
    (bus_for_each_dev) from [<c05ac734>] (bus_add_driver+0x104/0x20c)
    (bus_add_driver) from [<c05aece0>] (driver_register+0x78/0x10c)
    (driver_register) from [<c0103214>] (do_one_initcall+0x8c/0x430)
    (do_one_initcall) from [<c0f01328>] (kernel_init_freeable+0x3c8/0x4d0)
    (kernel_init_freeable) from [<c0ac3aa0>] (kernel_init+0x8/0x10c)
    (kernel_init) from [<c01010b4>] (ret_from_fork+0x14/0x20)

The PMU module seems to work fine on Exynos4412 SoCs, so the patch also
moves the interrupt definitions to exynos4210.dtsi and exynos4412.dtsi
respectively, to keep only the common part in exynos4.dtsi.

Fixes: 13efd80a ("ARM: dts: exynos: Add GPU/Mali 400 node to Exynos4")
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>

Switch to the "marvell,armada-38x-uart" driver variant to empty
the UART buffer before writing to the UART_LCR register.
Signed-off-by: NJoshua Scott <joshua.scott@alliedtelesis.co.nz>
Tested-by: NAndrew Lunn <andrew@lunn.ch>
Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>.
Cc: stable@vger.kernel.org
Fixes: 43e28ba8 ("ARM: dts: Use armada-370-xp as a base for armada-xp-98dx3236")
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>

Add display_subsystem, hdmi_phy, vop, and hdmi device nodes plus
a few hdmi pinctrl entries to allow for HDMI output.
Signed-off-by: NJustin Swartz <justin.swartz@risingedge.co.za>
[added assigned-clock settings for hdmiphy output]
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

iommu-cells obviously needs to start with a "#".
Signed-off-by: NJustin Swartz <justin.swartz@risingedge.co.za>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This reverts commit 288ceb85.

The commit assumes that the minnie panel is a AUO B101EAN01.1 (LVDS
interface), however it is a AUO B101EAN01.8 (eDP interface). The eDP
panel doesn't need the 200 ms delay.
Signed-off-by: NMatthias Kaehlcke <mka@chromium.org>
Reviewed-by: NEnric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This is the other half of the hacky solution from commit f497ab6b
("ARM: dts: rockchip: Configure BT_HOST_WAKE as wake-up signal on
veyron").  Specifically the LPM driver that the Broadcom Bluetooth
expects to have (but is missing in mainline) has two halves of the
equation: BT_HOST_WAKE and BT_DEV_WAKE.  The BT_HOST_WAKE (which was
handled in the previous commit) is the one that lets the Bluetooth
wake the system up.  The BT_DEV_WAKE (this patch) tells the Bluetooth
that it's OK to go into a low power mode.  That means we were burning
a bit of extra power in S3 without this patch.  Measurements are a bit
noisy, but it appears to be a few mA worth of difference.

NOTE: Though these pins don't do much on systems with Marvell
Bluetooth, downstream kernels set it on all veyron boards so we'll do
the same.
Signed-off-by: NDouglas Anderson <dianders@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add a node describing the vibration motor on the Fairphone 2.
Signed-off-by: NLuca Weiss <luca@z3ntu.xyz>
Signed-off-by: NAndy Gross <agross@kernel.org>

With commit d8e8fd0e ("mtd: rawnand: denali: decouple controller
and NAND chips"), the Denali NAND controller driver migrated to the
new controller/chip representation.

Update DT for it.

In the new binding, the number of connected chips are described in
DT instead of run-time probed.

I added just one chip to the reference boards, where we do not know
if the on-board NAND device is a single chip or multiple chips.
If we added too many chips into DT, it would end up with the timeout
error in nand_scan_ident().

I changed all the pinctrl properties to use the single CS.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Add nodes for GPU (Mali 400) to Exynos4210 and Exynos4412.  Describe the
GPU as much as possible however still few elements are missing:
1. Exynos4210 bus clock is not described in hardware manual therefore
   the IP gate clock was provided,
2. Exynos4412: Not sure what to do with CLK_G3D clock responsible for
   gating entire IP block (it is now being disabled as unused),
3. Regulator supplies on Trats board.

Limited testing on Odroid U3 (Exynos4412).
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>

Add nodes for GPU (Mali 400) to Exynos3250.  This is still limited and
not tested:
1. No dynamic voltage and frequency scaling,
2. Not sure what to do with CLK_G3D clock responsible for gating entire
   IP block (it is now being disabled as unused).
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>

The eMMC memory is supplied by LDO18 (PVDD_EMMC_1V8) and buck10
(PVDD_EMMCF_2V8), not by LDO10. The LDO10 (PVDD_PRE_1V8) supplies
instead VDDP_MMC pin of eMMC host interface and it is already marked as
always on.

This change only properly models the hardware and reflects in usage of
regulators.  There is no functional change because:
1. LDO18 cannot be turned off (e.g. by lack of consumers) because in
   off mode it is controlled by LDO18EN pin, which is pulled up by
   always-on regulator LDO2 (PVDD_APIO_1V8).
2. LDO10 is marked as always on so removing its consumer will not have
   effect.
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>

Add the PMIC regulator suspend configuration to entire Odroid
XU3/XU4/HC1 family of boards to reduce power usage during suspend.  The
configuration is based on vendor (Hardkernel) reference kernel with
additional buck9 suspend configuration (for USB hub suspend and proper
reset).

Energy consumption measurements from Marek Szyprowski during suspend to
RAM:
 - all at 5 V power supply,
 - before: next-20190620,
 - after: next-20190620 + this patch + suspend configuration for s2mps11
          regulator driver,

Board              | before [mA] | after [mA] |
Odroid HC1         |         120 |       7-10 |
Odroid XU4, sdcard |          88 |        6-9 |
Odroid XU4, eMMC   |         100 |        6-9 |
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>
Tested-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Tested-by: NAnand Moon <linux.amoon@gmail.com>

Add the PMIC regulator suspend configuration to Arndale Octa board to
reduce power usage during suspend and keep necessary regulators on.  The
configuration is based on vendor (Insignal) reference kernel and the
board datasheet.  Comparing to vendor kernel, additionally turn off in
suspend all regulators controlled by external pin (LDO3, LDO7, LDO18 and
buck10).

This is purely for hardware description because board does not support
Suspend to RAM and the S2MPS11 driver does not support
"regulator-on-in-suspend" property.
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>

The eMMC memory on Odroid XU3/XU4 boards is supplied by two regulators
LDO18 and buck10 (and LDO13 for the host interface).

However the Odroid HC1 board does not have eMMC connector so this
regulator does not have to be always on.
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>

Enable USBOTG1 support for evk board, it is dual-role function
port.
Signed-off-by: NPeter Chen <peter.chen@nxp.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Add imx7ulp USBOTG1 support.
Signed-off-by: NPeter Chen <peter.chen@nxp.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

The patch adds the following interfaces according the SMARC Spec 1.1
[1] and provided schematics:
 - SMARC SPI0/1
   Note: Since Kontron still uses silicon revisions below 1.3 they have
         add a spi-nor to implement Workaround #1 of erratum ERR006282.
 - SMARC SDIO
 - SMARC LCD
 - SMARC HDMI
 - SMARC Management pins
   Note: Kontron don't route all of these pins to the i.MX6, some are
         routed to the SoM CPLD.
 - SMARC GPIO
 - SMARC CSI Camera
   Note: As specified in [1] the data lanes are shared to cover the
         csi and the parallel case. The case depends on the baseboard so
         muxing the data lanes is not part of this patch.
 - SMARC I2S
 - SMARC Watchdog
   Note: The watchdog output pin is routed to the CPLD and the SMARC
         header. The CPLD performs a reset after a 30s timeout so we
         need to enable the watchdog per default.
 - SMARC module eeprom

Due to the lack of hardware not all of these interfaces are tesetd.

[1] https://sget.org/standards/smarcSigned-off-by: NMichael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: NMarco Felsch <m.felsch@pengutronix.de>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

According to the i.MX6UL/L RM, table 3.1 "ARM Cortex A7 domain interrupt
summary", the interrupts for the PWM[1-4] go from 83 to 86.

Fixes: b9901fe8 ("ARM: dts: imx6ul: add pwm[1-4] nodes")
Signed-off-by: NSébastien Szymanski <sebastien.szymanski@armadeus.com>
Reviewed-by: NFabio Estevam <festevam@gmail.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

These settings are needed to make the hardware operable.
Signed-off-by: NDaniel Mack <daniel@zonque.org>
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>

Careless oversight.
Signed-off-by: NDaniel Mack <daniel@zonque.org>
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>

The PEN2 line needs to be pulled up for the charger to enter high-current
mode. Do this with a static pull on the GPIO.
Signed-off-by: NDaniel Mack <daniel@zonque.org>
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>