1. 18 4月, 2014 1 次提交
  2. 04 4月, 2014 1 次提交
  3. 26 3月, 2014 1 次提交
  4. 25 3月, 2014 1 次提交
  5. 22 3月, 2014 1 次提交
  6. 20 3月, 2014 1 次提交
  7. 19 3月, 2014 2 次提交
  8. 13 3月, 2014 1 次提交
    • J
      ASoC: tlv320aic31xx: Add basic codec driver implementation · e00447fa
      Jyri Sarha 提交于
      This commit adds a bare bones driver support for TLV320AIC31XX family
      audio codecs. The driver adds basic stereo playback trough headphone
      and speaker outputs and mono capture trough microphone inputs.
      
      The driver is currently missing support at least for mini DSP features
      and jack detection. I have tested the driver only on TLV320AIC3111,
      but based on the data sheets TLV320AIC3100, TLV320AIC3110, and
      TLV320AIC3120 should work Ok too.
      
      The base for the implementation was taken from:
      git@gitorious.org:ti-codecs/ti-codecs.git ajitk/topics/k3.10.1-aic31xx
      -branch at commit 77504eba0294764e9e63b4a0c696b44db187cd13.
      Signed-off-by: NJyri Sarha <jsarha@ti.com>
      Signed-off-by: NMark Brown <broonie@linaro.org>
      e00447fa
  9. 06 3月, 2014 3 次提交
    • R
      ASoC: sirf: Add SiRF audio card · af12a31f
      Rongjun Ying 提交于
      This connects platform DAI, SiRF internal audio codec DAI  and
      SiRF auido port DAI together and works as a mach driver.
      Signed-off-by: NRongjun Ying <rongjun.ying@csr.com>
      Signed-off-by: NMark Brown <broonie@linaro.org>
      af12a31f
    • R
      ASoC: sirf: Add SiRF audio port driver is used by SiRF internal audio codec · a731e217
      Rongjun Ying 提交于
      This driver is used by SIRF internal audio codec.
      Use dedicated SiRF audio port TXFIFO and RXFIFO
      Supports two DMA channels for SiRF audio port TXFIFO and RXFIFO
      The audio port like as audio bus such as i2s.
      Signed-off-by: NRongjun Ying <rongjun.ying@csr.com>
      Signed-off-by: NMark Brown <broonie@linaro.org>
      a731e217
    • R
      ASoC: sirf: Add SiRF internal audio codec driver · f516e368
      Rongjun Ying 提交于
      SiRF internal audio codec is integrated in SiRF atlas6 and prima2 SoC.
      Features include:
      1. Stereo DAC and ADC with 16-bit resolution amd 48KHz sample rate
      2. Support headphone and/or speaker output
      3. Integrate headphone and speaker output amp
      4. Support LINE and MIC input
      5. Support single ended and differential input mode
      Signed-off-by: NRongjun Ying <rongjun.ying@csr.com>
      --v5:
      1. Drop all inlines.
      2. Reordering the Kconfig and Makefile
      3. Remove the sirf_audio_codec_reg_bits struct, use the new controls instead it.
      4. Add some SND_SOC_DAPM_OUT_DRV instead of HP and SPK enable driver
      5. Add audio codec clock supply instead of adc event callback
      6. Fixed playback and capture can't concurrent work bug.
      
      --
       .../devicetree/bindings/sound/sirf-audio-codec.txt |   17 +
       sound/soc/codecs/Kconfig                           |    5 +
       sound/soc/codecs/Makefile                          |    1 +
       sound/soc/codecs/sirf-audio-codec.c                |  533 ++++++++++++++++++++
       sound/soc/codecs/sirf-audio-codec.h                |   75 +++
       5 files changed, 631 insertions(+), 0 deletions(-)
       create mode 100644 Documentation/devicetree/bindings/sound/sirf-audio-codec.txt
       create mode 100644 sound/soc/codecs/sirf-audio-codec.c
       create mode 100644 sound/soc/codecs/sirf-audio-codec.h
      Signed-off-by: NMark Brown <broonie@linaro.org>
      f516e368
  10. 03 3月, 2014 1 次提交
  11. 27 2月, 2014 1 次提交
  12. 23 2月, 2014 4 次提交
  13. 15 2月, 2014 1 次提交
  14. 12 2月, 2014 2 次提交
  15. 11 2月, 2014 1 次提交
  16. 10 2月, 2014 3 次提交
  17. 06 2月, 2014 1 次提交
    • M
      ASoC: pcm512x: Add PCM512x driver · 5a3af129
      Mark Brown 提交于
      The PCM512x devices are a family of monolithic CMOS integrated circuits
      that include a stereo digital-to-analog converter and additional support
      circuitry.
      
      This is an initial driver which supports some core functionality for the
      device which covers common use cases but does not cover all features.
      Currently only slave clocking modes with automatic clock configuration
      are supported and most of the DSP configuration for the device is not
      enabled.
      Signed-off-by: NMark Brown <broonie@linaro.org>
      5a3af129
  18. 03 2月, 2014 1 次提交
  19. 28 1月, 2014 1 次提交
  20. 24 1月, 2014 1 次提交
  21. 13 1月, 2014 1 次提交
  22. 10 1月, 2014 1 次提交
    • N
      ASoC: fsl_esai: Add ESAI CPU DAI driver · 43d24e76
      Nicolin Chen 提交于
      This patch implements a device-tree-only CPU DAI driver for Freescale ESAI
      controller that supports:
      
       - 12 channels playback and 8 channels record.
         [ Some of the inner transmitters and receivers are sharing same group of
           pins. So the maxmium 12 output or 8 input channels are only valid if
           there is no pin conflict occurring to it. ]
      
       - Independent (asynchronous mode) or shared (synchronous mode) transmit and
         receive sections with separate or shared internal/external clocks and frame
         syncs, operating in Master or Slave mode.
         [ Current ALSA seems not to allow CPU DAI drivers to configure DAI format
           separately for PLAYBACK and CAPTURE. So this first version only supports
           the case that uses the same DAI format for both directions. ]
      
       - Various DAI formats: I2S, Left-Justified, Right-Justified, DSP-A and DSP-B.
      
       - Programmable word length (8, 16, 20 or 24bits)
      
       - Flexible selection between system clock or external oscillator as input
         clock source, programmable internal clock divider and frame sync generation.
      Signed-off-by: NNicolin Chen <Guangyu.Chen@freescale.com>
      Signed-off-by: NMark Brown <broonie@linaro.org>
      43d24e76
  23. 09 1月, 2014 1 次提交
  24. 07 1月, 2014 1 次提交
  25. 31 12月, 2013 2 次提交
  26. 19 12月, 2013 1 次提交
  27. 13 12月, 2013 1 次提交
    • S
      ASoC: tegra: update module reset list for Tegra124 · f1d6ff79
      Stephen Warren 提交于
      Tegra124 adds a number of extra modules into the configlink bus, which
      must be taken out of reset before the bus is used. Update the AHUB
      driver to know about these extra modules (the AHUB HW module hosts the
      configlink bus).
      Based-on-work-by: NArun Shamanna Lakshmi <aruns@nvidia.com>
      Based-on-work-by: NSonghee Baek <sbaek@nvidia.com>
      Signed-off-by: NStephen Warren <swarren@nvidia.com>
      Acked-by: NMark Brown <broonie@linaro.org>
      ---
      This patch depends on "ASoC: tegra: use reset framework" to compile,
      which is ack'd and slated to go through a (large) topic branch in the
      Tegra tree. So, we can either:
      
      a) Merge that Tegra topic branch into the ASoC tree, then apply this.
         Note that I haven't created the topic branch yet, since I'm still
         waiting for DMA dependencies to be applied.
      
      b) Apply this change to the Tegra tree too. This change isn't directly
         related to the changes in the Tegra tree; it just makes use of the new
         reset controller feature that's introduced there.
      f1d6ff79
  28. 12 12月, 2013 3 次提交