- 10 2月, 2021 11 次提交
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由 Ard Biesheuvel 提交于
The fcrypt implementation uses memcpy() to access the input and output buffers so there is no need to set an alignmask. Signed-off-by: NArd Biesheuvel <ardb@kernel.org> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Ard Biesheuvel 提交于
Instead of using an alignmask of 0x3 to ensure 32-bit alignment of the CAST6 input and output blocks, which propagates to mode drivers, and results in pointless copying on architectures that don't care about alignment, use the unaligned accessors, which will do the right thing on each respective architecture, avoiding the need for double buffering. Signed-off-by: NArd Biesheuvel <ardb@kernel.org> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Ard Biesheuvel 提交于
Instead of using an alignmask of 0x3 to ensure 32-bit alignment of the CAST5 input and output blocks, which propagates to mode drivers, and results in pointless copying on architectures that don't care about alignment, use the unaligned accessors, which will do the right thing on each respective architecture, avoiding the need for double buffering. Signed-off-by: NArd Biesheuvel <ardb@kernel.org> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Ard Biesheuvel 提交于
Instead of using an alignmask of 0x3 to ensure 32-bit alignment of the Camellia input and output blocks, which propagates to mode drivers, and results in pointless copying on architectures that don't care about alignment, use the unaligned accessors, which will do the right thing on each respective architecture, avoiding the need for double buffering. Signed-off-by: NArd Biesheuvel <ardb@kernel.org> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Ard Biesheuvel 提交于
Instead of using an alignmask of 0x3 to ensure 32-bit alignment of the Blowfish input and output blocks, which propagates to mode drivers, and results in pointless copying on architectures that don't care about alignment, use the unaligned accessors, which will do the right thing on each respective architecture, avoiding the need for double buffering. Signed-off-by: NArd Biesheuvel <ardb@kernel.org> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Ard Biesheuvel 提交于
Instead of using an alignmask of 0x3 to ensure 32-bit alignment of the Serpent input and output blocks, which propagates to mode drivers, and results in pointless copying on architectures that don't care about alignment, use the unaligned accessors, which will do the right thing on each respective architecture, avoiding the need for double buffering. Signed-off-by: NArd Biesheuvel <ardb@kernel.org> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Ard Biesheuvel 提交于
It is not trivial to trace back why exactly the tnepres variant of serpent was added ~17 years ago - Google searches come up mostly empty, but it seems to be related with the 'kerneli' version, which was based on an incorrect interpretation of the serpent spec. In other words, nobody is likely to care anymore today, so let's get rid of it. Signed-off-by: NArd Biesheuvel <ardb@kernel.org> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Ard Biesheuvel 提交于
The Michael MIC driver uses the cra_alignmask to ensure that pointers presented to its update and finup/final methods are 32-bit aligned. However, due to the way the shash API works, this is no guarantee that the 32-bit reads occurring in the update method are also aligned, as the size of the buffer presented to update may be of uneven length. For instance, an update() of 3 bytes followed by a misaligned update() of 4 or more bytes will result in a misaligned access using an accessor that is not suitable for this. On most architectures, this does not matter, and so setting the cra_alignmask is pointless. On architectures where this does matter, setting the cra_alignmask does not actually solve the problem. So let's get rid of the cra_alignmask, and use unaligned accessors instead, where appropriate. Cc: <stable@vger.kernel.org> Signed-off-by: NArd Biesheuvel <ardb@kernel.org> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Jan Henrik Weinstock 提交于
Ensure cooldown period tolerance of 1% is actually accounted for. Fixes: ca3bff70 ("hwrng: timeriomem - Improve performance...") Signed-off-by: NJan Henrik Weinstock <jan.weinstock@rwth-aachen.de> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Geert Uytterhoeven 提交于
The Marvell OcteonTX2 CPT physical function PCI device is present only on OcteonTx2 SoC, and not available as an independent PCIe endpoint. Hence add a dependency on ARCH_THUNDER2, to prevent asking the user about this driver when configuring a kernel without OcteonTx2 platform support. Fixes: 5e8ce833 ("crypto: marvell - add Marvell OcteonTX2 CPT PF driver") Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux由 Herbert Xu 提交于
Pull change from arm64 tree that's needed for crypto arm changes.
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- 05 2月, 2021 4 次提交
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由 Florian Fainelli 提交于
It is currently possible to build CONFIG_HW_RANDOM_PPC4XX=y with CONFIG_HW_RANDOM=m which would lead to the inability of linking with devm_hwrng_{register,unregister}. We cannot have the framework modular and the consumer of that framework built-in, so make that dependency explicit. Reported-by: Nkernel test robot <lkp@intel.com> Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Herbert Xu 提交于
The crypto octeontx2 driver depends on the mbox code in the network tree. It tries to select the MBOX Kconfig option but that option itself depends on many other options which are not selected, e.g., CONFIG_NET_VENDOR_MARVELL. It would be inappropriate to select them all as randomly prompting the user for network options which would oterhwise be disabled just because a crypto driver has been enabled makes no sense. This patch fixes this by adding a dependency on NET_VENDOR_MARVELL. This makes the crypto driver invisible if the network option is off. If the crypto driver must be visible even without the network stack then the shared mbox code should be moved out of drivers/net. Reported-by: NRandy Dunlap <rdunlap@infradead.org> Reported-by: Nkernel test robot <lkp@intel.com> Fixes: 5e8ce833 ("crypto: marvell - add Marvell OcteonTX2 CPT...") Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au> Acked-by: Randy Dunlap <rdunlap@infradead.org> # build-tested Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Dan Carpenter 提交于
The "num_vec" has to be signed for the error handling to work. Fixes: 19d8e8c7 ("crypto: octeontx2 - add virtual function driver support") Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 dingsenjie 提交于
allocted -> allocated Signed-off-by: Ndingsenjie <dingsenjie@yulong.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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- 04 2月, 2021 1 次提交
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由 Ard Biesheuvel 提交于
Add a macro cond_yield that branches to a specified label when called if the TIF_NEED_RESCHED flag is set and decreasing the preempt count would make the task preemptible again, resulting in a schedule to occur. This can be used by kernel mode SIMD code that keeps a lot of state in SIMD registers, which would make chunking the input in order to perform the cond_resched() check from C code disproportionately costly. Signed-off-by: NArd Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20210203113626.220151-2-ardb@kernel.orgSigned-off-by: NWill Deacon <will@kernel.org>
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- 29 1月, 2021 11 次提交
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由 Ard Biesheuvel 提交于
Salsa20 is not used anywhere in the kernel, is not suitable for disk encryption, and widely considered to have been superseded by ChaCha20. So let's remove it. Signed-off-by: NArd Biesheuvel <ardb@kernel.org> Acked-by: NMike Snitzer <snitzer@redhat.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Ard Biesheuvel 提交于
Tiger is never referenced anywhere in the kernel, and unlikely to be depended upon by userspace via AF_ALG. So let's remove it. Signed-off-by: NArd Biesheuvel <ardb@kernel.org> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Ard Biesheuvel 提交于
RIPE-MD 320 is never referenced anywhere in the kernel, and unlikely to be depended upon by userspace via AF_ALG. So let's remove it Signed-off-by: NArd Biesheuvel <ardb@kernel.org> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Ard Biesheuvel 提交于
RIPE-MD 256 is never referenced anywhere in the kernel, and unlikely to be depended upon by userspace via AF_ALG. So let's remove it Signed-off-by: NArd Biesheuvel <ardb@kernel.org> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Ard Biesheuvel 提交于
RIPE-MD 128 is never referenced anywhere in the kernel, and unlikely to be depended upon by userspace via AF_ALG. So let's remove it. Signed-off-by: NArd Biesheuvel <ardb@kernel.org> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Herbert Xu 提交于
The cesa driver mixes use of iomem pointers and normal kernel pointers. Sometimes it uses memcpy_toio/memcpy_fromio on both while other times it would use straight memcpy on both, through the sg_pcopy_* helpers. This patch fixes this by adding a new field sram_pool to the engine for the normal pointer case which then allows us to use the right interface depending on the value of engine->pool. Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Christophe Leroy 提交于
While ctr(aes) requires the use of a special descriptor on SEC2 (see commit 70d355cc ("crypto: talitos - fix ctr-aes-talitos")), that special descriptor doesn't work on SEC1, see commit e738c5f1 ("powerpc/8xx: Add DT node for using the SEC engine of the MPC885"). However, the common nonsnoop descriptor works properly on SEC1 for ctr(aes). Add a second template for ctr(aes) that will be registered only on SEC1. Fixes: 70d355cc ("crypto: talitos - fix ctr-aes-talitos") Signed-off-by: NChristophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Christophe Leroy 提交于
Talitos Security Engine AESU considers any input data size that is not a multiple of 16 bytes to be an error. This is not a problem in general, except for Counter mode that is a stream cipher and can have an input of any size. Test Manager for ctr(aes) fails on 4th test vector which has a length of 499 while all previous vectors which have a 16 bytes multiple length succeed. As suggested by Freescale, round up the input data length to the nearest 16 bytes. Fixes: 5e75ae1b ("crypto: talitos - add new crypto modes") Signed-off-by: NChristophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Hui Tang 提交于
Uacce SysFS support more algorithms inqury such as 'ecdh/ecdsa/sm2/x25519/x448' Signed-off-by: NHui Tang <tanghui20@huawei.com> Reviewed-by: NZaibo Xu <xuzaibo@huawei.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Hui Tang 提交于
1.One CE error is detecting timeout of generating a random number. 2.Another is detecting timeout of SVA prefetching address. Signed-off-by: NHui Tang <tanghui20@huawei.com> Reviewed-by: NZaibo Xu <xuzaibo@huawei.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Hui Tang 提交于
Delete 'HPRE_RAS_ECC1BIT_TH' register setting of hpre, since register 'QM_RAS_CE_THRESHOLD' of qm has done this work. Signed-off-by: NHui Tang <tanghui20@huawei.com> Reviewed-by: NZaibo Xu <xuzaibo@huawei.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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- 22 1月, 2021 13 次提交
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由 Ard Biesheuvel 提交于
Taking ownership of the FPU in kernel mode disables preemption, and this may result in excessive scheduling blackouts if the size of the data being processed on the FPU is unbounded. Given that taking and releasing the FPU is cheap these days on x86, we can limit the impact of this issue easily for skcipher implementations, by moving the FPU begin/end calls inside the skcipher walk processing loop. Considering that skcipher walks operate on at most one page at a time, doing so fully mitigates this issue. This also permits the skcipher walk logic to use non-atomic kmalloc() calls etc so we can change the 'atomic' bool argument in the calls to skcipher_walk_virt() to false as well. Signed-off-by: NArd Biesheuvel <ardb@kernel.org> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Ard Biesheuvel 提交于
Indirect calls are very expensive on x86, so use a static call to set the system-wide AES-NI/CTR asm helper. Signed-off-by: NArd Biesheuvel <ardb@kernel.org> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Ovidiu Panait 提交于
src_size and aad_size are defined as u32, so the following expressions are currently being evaluated using 32-bit arithmetic: bit_len = src_size * 8; ... bit_len = aad_size * 8; However, bit_len is used afterwards in a context that expects a valid 64-bit value (the lower and upper 32-bit words of bit_len are extracted and written to hw). In order to make sure the correct bit length is generated and the 32-bit multiplication does not wrap around, cast src_size and aad_size to u64. Signed-off-by: NOvidiu Panait <ovidiu.panait@windriver.com> Acked-by: NDaniele Alessandrelli <daniele.alessandrelli@intel.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Jason A. Donenfeld 提交于
With no mod_exit function, users are unable to unload the module after use. I'm not aware of any reason why module unloading should be prohibited for this one, so this commit simply adds an empty exit function. Reported-and-tested-by: NJohn Donnelly <john.p.donnelly@oracle.com> Acked-by: NArd Biesheuvel <ardb@kernel.org> Signed-off-by: NJason A. Donenfeld <Jason@zx2c4.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Srujana Challa 提交于
CPT offload module utilises the linux crypto framework to offload crypto processing. This patch registers supported algorithms by calling registration functions provided by the kernel crypto API. The module currently supports: - AES block cipher in CBC,ECB and XTS mode. - 3DES block cipher in CBC and ECB mode. - AEAD algorithms. authenc(hmac(sha1),cbc(aes)), authenc(hmac(sha256),cbc(aes)), authenc(hmac(sha384),cbc(aes)), authenc(hmac(sha512),cbc(aes)), authenc(hmac(sha1),ecb(cipher_null)), authenc(hmac(sha256),ecb(cipher_null)), authenc(hmac(sha384),ecb(cipher_null)), authenc(hmac(sha512),ecb(cipher_null)), rfc4106(gcm(aes)). Signed-off-by: NSuheil Chandran <schandran@marvell.com> Signed-off-by: NLukasz Bartosik <lbartosik@marvell.com> Signed-off-by: NSrujana Challa <schalla@marvell.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Srujana Challa 提交于
Attach LFs to CPT VF to process the crypto requests and register LF interrupts. Signed-off-by: NSuheil Chandran <schandran@marvell.com> Signed-off-by: NLukasz Bartosik <lbartosik@marvell.com> Signed-off-by: NSrujana Challa <schalla@marvell.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Srujana Challa 提交于
Add support for the Marvell OcteonTX2 CPT virtual function driver. This patch includes probe, PCI specific initialization and interrupt handling. Signed-off-by: NSuheil Chandran <schandran@marvell.com> Signed-off-by: NLukasz Bartosik <lbartosik@marvell.com> Signed-off-by: NSrujana Challa <schalla@marvell.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Srujana Challa 提交于
Adds support to get engine capabilities and adds a new mailbox to share capabilities with VF driver. Signed-off-by: NSuheil Chandran <schandran@marvell.com> Signed-off-by: NSrujana Challa <schalla@marvell.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Srujana Challa 提交于
CPT RVU Local Functions(LFs) needs to be attached to the PF/VF to submit the instructions to CPT. This patch adds the interface to initialize and attach the LFs. It also adds interface to register the LF's interrupts. Signed-off-by: NSuheil Chandran <schandran@marvell.com> Signed-off-by: NLukasz Bartosik <lbartosik@marvell.com> Signed-off-by: NSrujana Challa <schalla@marvell.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Srujana Challa 提交于
CPT includes microcoded GigaCypher symmetric engines(SEs), IPsec symmetric engines(IEs), and asymmetric engines (AEs). Each engine receives CPT instructions from the engine groups it has subscribed to. This patch loads microcode, configures three engine groups(one for SEs, one for IEs and one for AEs), and configures all engines. Signed-off-by: NSuheil Chandran <schandran@marvell.com> Signed-off-by: NLukasz Bartosik <lbartosik@marvell.com> Signed-off-by: NSrujana Challa <schalla@marvell.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Srujana Challa 提交于
Adds 'sriov_configure' to enable/disable virtual functions (VFs). Also Initializes VF<=>PF mailbox IRQs, register handlers for processing these mailbox messages. Admin function (AF) handles resource allocation and configuration for PFs and their VFs. PFs request the AF directly, via mailboxes. Unlike PFs, VFs cannot send a mailbox request directly. A VF sends mailbox messages to its parent PF, with which it shares a mailbox region. The PF then forwards these messages to the AF. After handling the request, the AF sends a response back to the VF, through the PF. This patch adds support for this 'VF <=> PF <=> AF' mailbox communication. Signed-off-by: NSuheil Chandran <schandran@marvell.com> Signed-off-by: NLukasz Bartosik <lbartosik@marvell.com> Signed-off-by: NSrujana Challa <schalla@marvell.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Srujana Challa 提交于
In the resource virtualization unit (RVU) each of the PF and AF (admin function) share a 64KB of reserved memory region for communication. This patch initializes PF <=> AF mailbox IRQs, registers handlers for processing these communication messages. Signed-off-by: NSuheil Chandran <schandran@marvell.com> Signed-off-by: NLukasz Bartosik <lbartosik@marvell.com> Signed-off-by: NSrujana Challa <schalla@marvell.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Srujana Challa 提交于
Adds skeleton for the Marvell OcteonTX2 CPT physical function driver which includes probe, PCI specific initialization and hardware register defines. RVU defines are present in AF driver (drivers/net/ethernet/marvell/octeontx2/af), header files from AF driver are included here to avoid duplication. Signed-off-by: NSuheil Chandran <schandran@marvell.com> Signed-off-by: NLukasz Bartosik <lbartosik@marvell.com> Signed-off-by: NSrujana Challa <schalla@marvell.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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