1. 18 3月, 2019 1 次提交
  2. 16 2月, 2019 1 次提交
  3. 08 2月, 2019 1 次提交
  4. 06 2月, 2019 1 次提交
    • B
      IB/mlx5: Do not use hw_access_flags for be and CPU data · bf3b4f06
      Bart Van Assche 提交于
      Avoid that sparse reports the following for the mlx5 driver:
      
      drivers/infiniband/hw/mlx5/qp.c:2671:34: warning: invalid assignment: |=
      drivers/infiniband/hw/mlx5/qp.c:2671:34:    left side has type restricted __be32
      drivers/infiniband/hw/mlx5/qp.c:2671:34:    right side has type int
      drivers/infiniband/hw/mlx5/qp.c:2679:34: warning: invalid assignment: |=
      drivers/infiniband/hw/mlx5/qp.c:2679:34:    left side has type restricted __be32
      drivers/infiniband/hw/mlx5/qp.c:2679:34:    right side has type int
      drivers/infiniband/hw/mlx5/qp.c:2680:34: warning: invalid assignment: |=
      drivers/infiniband/hw/mlx5/qp.c:2680:34:    left side has type restricted __be32
      drivers/infiniband/hw/mlx5/qp.c:2680:34:    right side has type int
      drivers/infiniband/hw/mlx5/qp.c:2684:34: warning: invalid assignment: |=
      drivers/infiniband/hw/mlx5/qp.c:2684:34:    left side has type restricted __be32
      drivers/infiniband/hw/mlx5/qp.c:2684:34:    right side has type int
      drivers/infiniband/hw/mlx5/qp.c:2686:28: warning: cast from restricted __be32
      drivers/infiniband/hw/mlx5/qp.c:2686:28: warning: incorrect type in argument 1 (different base types)
      drivers/infiniband/hw/mlx5/qp.c:2686:28:    expected unsigned int [usertype] val
      drivers/infiniband/hw/mlx5/qp.c:2686:28:    got restricted __be32 [usertype]
      drivers/infiniband/hw/mlx5/qp.c:2686:28: warning: cast from restricted __be32
      drivers/infiniband/hw/mlx5/qp.c:2686:28: warning: cast from restricted __be32
      drivers/infiniband/hw/mlx5/qp.c:2686:28: warning: cast from restricted __be32
      drivers/infiniband/hw/mlx5/qp.c:2686:28: warning: cast from restricted __be32
      
      This patch does not change any functionality.
      
      Fixes: a60109dc ("IB/mlx5: Add support for extended atomic operations")
      Signed-off-by: NBart Van Assche <bvanassche@acm.org>
      Acked-by: NLeon Romanovsky <leonro@mellanox.com>
      Signed-off-by: NJason Gunthorpe <jgg@mellanox.com>
      bf3b4f06
  5. 05 2月, 2019 1 次提交
  6. 22 1月, 2019 1 次提交
  7. 11 1月, 2019 1 次提交
  8. 03 1月, 2019 1 次提交
  9. 19 12月, 2018 2 次提交
  10. 15 12月, 2018 1 次提交
  11. 12 12月, 2018 1 次提交
  12. 08 12月, 2018 1 次提交
  13. 05 12月, 2018 1 次提交
  14. 30 11月, 2018 1 次提交
  15. 22 11月, 2018 3 次提交
  16. 17 10月, 2018 4 次提交
  17. 16 10月, 2018 1 次提交
  18. 04 10月, 2018 1 次提交
  19. 28 9月, 2018 1 次提交
  20. 27 9月, 2018 1 次提交
  21. 26 9月, 2018 8 次提交
  22. 22 9月, 2018 3 次提交
  23. 13 9月, 2018 1 次提交
  24. 07 9月, 2018 1 次提交
  25. 05 9月, 2018 1 次提交
    • M
      IB/mlx5: Change TX affinity assignment in RoCE LAG mode · c6a21c38
      Majd Dibbiny 提交于
      In the current code, the TX affinity is per RoCE device, which can cause
      unfairness between different contexts. e.g. if we open two contexts, and
      each open 10 QPs concurrently, all of the QPs of the first context might
      end up on the first port instead of distributed on the two ports as
      expected
      
      To overcome this unfairness between processes, we maintain per device TX
      affinity, and per process TX affinity.
      
      The allocation algorithm is as follow:
      
      1. Hold two tx_port_affinity atomic variables, one per RoCE device and one
         per ucontext. Both initialized to 0.
      
      2. In mlx5_ib_alloc_ucontext do:
       2.1. ucontext.tx_port_affinity = device.tx_port_affinity
       2.2. device.tx_port_affinity += 1
      
      3. In modify QP INIT2RST:
       3.1. qp.tx_port_affinity = ucontext.tx_port_affinity % MLX5_PORT_NUM
       3.2. ucontext.tx_port_affinity += 1
      Signed-off-by: NMajd Dibbiny <majd@mellanox.com>
      Reviewed-by: NMoni Shoua <monis@mellanox.com>
      Signed-off-by: NLeon Romanovsky <leonro@mellanox.com>
      Signed-off-by: NJason Gunthorpe <jgg@mellanox.com>
      c6a21c38