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  1. 09 5月, 2015 2 次提交
    • K
      thermal: ti-soc-thermal: OMAP5: Implement Workaround for Errata i813 · e9a90d04
      由 Keerthy 提交于 
      DESCRIPTION

Spurious Thermal Alert: Talert can happen randomly while the device remains
under the temperature limit defined for this event to trig. This spurious
event is caused by a incorrect re-synchronization between clock domains.
The comparison between configured threshold and current temperature value
can happen while the value is transitioning (metastable), thus causing
inappropriate event generation. No spurious event occurs as long as the
threshold value stays unchanged. Spurious event can be generated while a
thermal alert threshold is modified in
CONTROL_BANDGAP_THRESHOLD_MPU/GPU/CORE/DSPEVE/IVA_n.

WORKAROUND

Spurious event generation can be avoided by performing following sequence
when the threshold is modified:
1. Mask the hot/cold events at the thermal IP level.
2. Modify Threshold.
3. Unmask the hot/cold events at the thermal IP level.
Signed-off-by: NKeerthy <j-keerthy@ti.com>
Signed-off-by: NEduardo Valentin <edubezval@gmail.com>
      e9a90d04
    • K
      thermal: ti-soc-thermal: dra7: Implement Workaround for Errata i814 · 79010636
      由 Keerthy 提交于 
      Bandgap Temperature read Dtemp can be corrupted

DESCRIPTION
        Read accesses to registers listed below can be corrupted due to
	incorrect resynchronization between clock domains.

        Read access to registers below can be corrupted :
                • CTRL_CORE_DTEMP_MPU/GPU/CORE/DSPEVE/IVA_n (n = 0 to 4)
        • CTRL_CORE_TEMP_SENSOR_MPU/GPU/CORE/DSPEVE/IVA_n

WORKAROUND
    Multiple reads to CTRL_CORE_TEMP_SENSOR_MPU/GPU/CORE/DSPEVE/IVA[9:0]:
    BGAP_DTEMPMPU/GPU/CORE/DSPEVE/IVA is needed to discard false value and
    read right value:
       1. Perform two successive reads to BGAP_DTEMP bit field.
               (a) If read1 returns Val1 and read2 returns Val1, then
       	right value is Val1.
               (b) If read1 returns Val1, read 2 returns Val2, a third
       	read is needed.
       2. Perform third read
               (a) If read3 returns Val2 then right value is Val2.
               (b) If read3 returns Val3, then right value is Val3.

    The above in gist means if val1 and val2 are the same then we can go
    ahead with that value else we need a third read which will be right
    since synchronization will be complete by then.
Signed-off-by: NKeerthy <j-keerthy@ti.com>
Signed-off-by: NEduardo Valentin <edubezval@gmail.com>
      79010636
  3. 25 2月, 2015 1 次提交
  5. 01 7月, 2014 1 次提交
  7. 07 5月, 2014 1 次提交
    • P
      thermal: ti-soc-thermal: clk_round_rate() can return a zero upon error · c68789e5
      由 Paul Walmsley 提交于 
      Treat both negative and zero return values from clk_round_rate() as
errors.  This is needed since subsequent patches will convert
clk_round_rate()'s return value to be an unsigned type, rather than a
signed type, since some clock sources can generate rates higher than
(2^31)-1 Hz.

Eventually, when calling clk_round_rate(), only a return value of zero
will be considered a error.  All other values will be considered valid
rates.  The comparison against values less than 0 is kept to preserve
the correct behavior in the meantime.

This patch also gets rid of a comparison between unsigned and signed
values; a side-benefit.
Signed-off-by: NPaul Walmsley <pwalmsley@nvidia.com>
Cc: Eduardo Valentin <eduardo.valentin@ti.com>
Cc: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: NEduardo Valentin <edubezval@gmail.com>
      c68789e5
  9. 08 4月, 2014 1 次提交
  11. 29 8月, 2013 1 次提交
  13. 08 7月, 2013 1 次提交
    • E
      thermal: ti-soc-thermal: use standard GPIO DT bindings · 57d16171
      由 Eduardo Valentin 提交于 
      This change updates the ti-soc-thermal driver to use
standard GPIO DT bindings to read the GPIO number associated
to thermal shutdown IRQ, in case the device features it.

Previously, the code was using a specific DT bindings.
As now OMAP supports the standard way to model GPIOs,
there is no point in having a ti specific binding.

Cc: Zhang Rui <rui.zhang@intel.com>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: linux-pm@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: devicetree-discuss@lists.ozlabs.org
Signed-off-by: NEduardo Valentin <eduardo.valentin@ti.com>
      57d16171
  15. 13 6月, 2013 3 次提交
  17. 28 5月, 2013 1 次提交
    • E
      thermal: introduce TI SoC thermal driver · eb982001
      由 Eduardo Valentin 提交于 
      This patch moves the ti-soc-thermal driver out of
the staging tree to the thermal tree.

Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Rob Landley <rob@landley.net>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Zhang Rui <rui.zhang@intel.com>
Cc: Eduardo Valentin <eduardo.valentin@ti.com>
Cc: J Keerthy <j-keerthy@ti.com>
Cc: Radhesh Fadnis <radhesh.fadnis@ti.com>
Cc: Cyril Roelandt <tipecaml@gmail.com>
Cc: devicetree-discuss@lists.ozlabs.org
Cc: linux-doc@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: devel@driverdev.osuosl.org
Cc: linux-pm@vger.kernel.org
Signed-off-by: NEduardo Valentin <eduardo.valentin@ti.com>
Signed-off-by: NZhang Rui <rui.zhang@intel.com>
      eb982001
  19. 09 4月, 2013 2 次提交
  21. 02 4月, 2013 4 次提交
  23. 26 3月, 2013 11 次提交
  25. 16 3月, 2013 11 次提交