1. 27 4月, 2018 1 次提交
    • I
      net/mlx5: Fix mlx5_get_vector_affinity function · 6082d9c9
      Israel Rukshin 提交于
      Adding the vector offset when calling to mlx5_vector2eqn() is wrong.
      This is because mlx5_vector2eqn() checks if EQ index is equal to vector number
      and the fact that the internal completion vectors that mlx5 allocates
      don't get an EQ index.
      
      The second problem here is that using effective_affinity_mask gives the same
      CPU for different vectors.
      This leads to unmapped queues when calling it from blk_mq_rdma_map_queues().
      This doesn't happen when using affinity_hint mask.
      
      Fixes: 2572cf57 ("mlx5: fix mlx5_get_vector_affinity to start from completion vector 0")
      Fixes: 05e0cc84 ("net/mlx5: Fix get vector affinity helper function")
      Signed-off-by: NIsrael Rukshin <israelr@mellanox.com>
      Reviewed-by: NMax Gurtovoy <maxg@mellanox.com>
      Reviewed-by: NSagi Grimberg <sagi@grimberg.me>
      6082d9c9
  2. 06 4月, 2018 2 次提交
  3. 05 4月, 2018 6 次提交
  4. 04 4月, 2018 2 次提交
  5. 22 3月, 2018 1 次提交
  6. 20 3月, 2018 3 次提交
  7. 15 3月, 2018 2 次提交
    • M
      IB/mlx5: Fix cleanup order on unload · 42cea83f
      Mark Bloch 提交于
      On load we create private CQ/QP/PD in order to be used by UMR, we create
      those resources after we register ourself as an IB device, and we destroy
      them after we unregister as an IB device. This was changed by commit
      16c1975f ("IB/mlx5: Create profile infrastructure to add and remove
      stages") which moved the destruction before we unregistration. This
      allowed to trigger an invalid memory access when unloading mlx5_ib while
      there are open resources:
      
      BUG: unable to handle kernel paging request at 00000001002c012c
      ...
      Call Trace:
       mlx5_ib_post_send_wait+0x75/0x110 [mlx5_ib]
       __slab_free+0x9a/0x2d0
       delay_time_func+0x10/0x10 [mlx5_ib]
       unreg_umr.isra.15+0x4b/0x50 [mlx5_ib]
       mlx5_mr_cache_free+0x46/0x150 [mlx5_ib]
       clean_mr+0xc9/0x190 [mlx5_ib]
       dereg_mr+0xba/0xf0 [mlx5_ib]
       ib_dereg_mr+0x13/0x20 [ib_core]
       remove_commit_idr_uobject+0x16/0x70 [ib_uverbs]
       uverbs_cleanup_ucontext+0xe8/0x1a0 [ib_uverbs]
       ib_uverbs_cleanup_ucontext.isra.9+0x19/0x40 [ib_uverbs]
       ib_uverbs_remove_one+0x162/0x2e0 [ib_uverbs]
       ib_unregister_device+0xd4/0x190 [ib_core]
       __mlx5_ib_remove+0x2e/0x40 [mlx5_ib]
       mlx5_remove_device+0xf5/0x120 [mlx5_core]
       mlx5_unregister_interface+0x37/0x90 [mlx5_core]
       mlx5_ib_cleanup+0xc/0x225 [mlx5_ib]
       SyS_delete_module+0x153/0x230
       do_syscall_64+0x62/0x110
       entry_SYSCALL_64_after_hwframe+0x21/0x86
      ...
      
      We restore the original behavior by breaking the UMR stage into two parts,
      pre and post IB registration stages, this way we can restore the original
      functionality and maintain clean separation of logic between stages.
      
      Fixes: 16c1975f ("IB/mlx5: Create profile infrastructure to add and remove stages")
      Signed-off-by: NMark Bloch <markb@mellanox.com>
      Signed-off-by: NLeon Romanovsky <leonro@mellanox.com>
      Signed-off-by: NDoug Ledford <dledford@redhat.com>
      42cea83f
    • I
      IB/mlx5: Maintain a single emergency page · c44ef998
      Ilya Lesokhin 提交于
      The mlx5 driver needs to be able to issue invalidation to ODP MRs
      even if it cannot allocate memory. To this end it preallocates
      emergency pages to use when the situation arises.
      
      This flow should be extremely rare enough, that we don't need
      to worry about contention and therefore a single emergency page
      is good enough.
      Signed-off-by: NIlya Lesokhin <ilyal@mellanox.com>
      Signed-off-by: NLeon Romanovsky <leon@kernel.org>
      Signed-off-by: NDoug Ledford <dledford@redhat.com>
      c44ef998
  8. 07 3月, 2018 5 次提交
  9. 01 3月, 2018 1 次提交
  10. 24 2月, 2018 6 次提交
  11. 20 1月, 2018 1 次提交
  12. 19 1月, 2018 1 次提交
  13. 12 1月, 2018 2 次提交
  14. 11 1月, 2018 1 次提交
  15. 09 1月, 2018 6 次提交