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  1. 31 7月, 2014 1 次提交
    • H
      MIPS: Add Loongson-3B support · e7841be5
      由 Huacai Chen 提交于 
      Loongson-3B is a 8-cores processor. In general it looks like there are
two Loongson-3A integrated in one chip: 8 cores are separated into two
groups (two NUMA node), each node has its own local memory.

Of course there are some differences between one Loongson-3B and two
Loongson-3A. E.g., the base addresses of IPI registers of each node are
not the same; Loongson-3A use ChipConfig register to enable/disable
clock, but Loongson-3B use FreqControl register instead.

There are two revision of Loongson-3B, the first revision is called as
Loongson-3B1000, whose frequency is 1GHz and has a PRid 0x6306, the
second revision is called as Loongson-3B1500, whose frequency is 1.5GHz
and has a PRid 0x6307. Both revisions has a bug that clock cannot be
disabled at runtime, but this will be fixed in future.
Signed-off-by: NHuacai Chen <chenhc@lemote.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/7188/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      e7841be5
  3. 30 5月, 2014 1 次提交
  5. 23 5月, 2014 1 次提交
  7. 01 4月, 2014 2 次提交
  9. 27 3月, 2014 5 次提交
  11. 07 3月, 2014 1 次提交
  13. 25 1月, 2014 1 次提交
  15. 23 1月, 2014 7 次提交
  17. 19 9月, 2013 1 次提交
  19. 04 9月, 2013 1 次提交
  21. 26 8月, 2013 1 次提交
  23. 01 7月, 2013 1 次提交
    • R
      MIPS: Get rid of MIPS I flag and test macros. · 1990e542
      由 Ralf Baechle 提交于 
      MIPS I is the ancestor of all MIPS ISA and architecture variants.  Anything
ever build in the MIPS empire is either MIPS I or at least contains MIPS I.
If it's running Linux, that is.

So there is little point in having cpu_has_mips_1 because it will always
evaluate as true - though usually only at runtime.  Thus there is no
point in having the MIPS_CPU_ISA_I ISA flag, so get rid of it.

Little complication: traps.c was using a test for a pure MIPS I ISA as
a test for an R3000-style cp0.  To deal with that, use a check for
cpu_has_3kex or cpu_has_4kex instead.

cpu_has_3kex is a new macro.  At the moment its default implementation is
!cpu_has_4kex but this may eventually change if Linux is ever going to
support the oddball MIPS processors R6000 and R8000 so users of either
of these macros should not make any assumptions.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/5551/
      1990e542
  25. 19 2月, 2013 1 次提交
  27. 17 2月, 2013 1 次提交
  29. 01 2月, 2013 1 次提交
  31. 26 11月, 2012 1 次提交
  33. 11 10月, 2012 2 次提交
  35. 14 9月, 2012 2 次提交
  37. 23 7月, 2012 1 次提交
    • K
      MIPS: Add CPU support for Loongson1B · 2fa36399
      由 Kelvin Cheung 提交于 
      Loongson 1B is a 32-bit SoC designed by Institute of Computing Technology
(ICT) and the Chinese Academy of Sciences (CAS), which implements the
MIPS32 release 2 instruction set.

[ralf@linux-mips.org: But which is not strictly a MIPS32 compliant device
which also is why it identifies itself with the Legacy Vendor ID in the
PrID register.  When applying the patch I shoveled some code around to
keep things in alphabetical order and avoid forward declarations.]
Signed-off-by: NKelvin Cheung <keguang.zhang@gmail.com>
Cc: To: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: wuzhangjin@gmail.com
Cc: zhzhl555@gmail.com
Cc: Kelvin Cheung <keguang.zhang@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/3976/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      2fa36399
  39. 19 7月, 2012 1 次提交
  41. 07 7月, 2012 1 次提交
  43. 08 12月, 2011 3 次提交
  45. 25 10月, 2011 1 次提交
  47. 19 5月, 2011 1 次提交
  49. 06 4月, 2011 1 次提交