1. 30 6月, 2005 2 次提交
  2. 29 6月, 2005 1 次提交
  3. 28 6月, 2005 2 次提交
  4. 27 6月, 2005 2 次提交
    • R
      [PATCH] Serial: Split 8250 port table · ec9f47cd
      Russell King 提交于
      Add separate files for the different 8250 ISA-based serial boards.
      
      Looking across all the various architectures, it seems reasonable that
      we can key the availability of the configuration options for these
      beasts to the bus-related symbols (iow, CONFIG_ISA).  We also standardise
      the base baud/uart clock rate for these boards - I'm sure that isn't
      architecture specific, but is solely dependent on the crystal fitted
      on the board (which should be the same no matter what type of machine
      its fitted into.)
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      ec9f47cd
    • R
      [PATCH] Serial: Remove {un,}register_serial from 68328serial.c · addcc4a1
      Russell King 提交于
      68328serial.c does not make use of register_serial/unregister_serial,
      which is traditionally used to register 8250-compatible UARTs with
      the 8250-compatible serial driver.
      
      Acked-by: David McCullough
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      addcc4a1
  5. 26 6月, 2005 4 次提交
  6. 25 6月, 2005 2 次提交
  7. 24 6月, 2005 3 次提交
  8. 23 6月, 2005 2 次提交
  9. 22 6月, 2005 5 次提交
    • B
      [PATCH] ioc4: PCI bus speed detection · d4c477ca
      Brent Casavant 提交于
      Several hardware features of SGI's IOC4 I/O controller chip require
      timing-related driver calculations dependent upon the PCI bus speed.  This
      patch enables the core IOC4 driver code to detect the actual bus speed and
      store a value that can later be used by the IOC4 subdrivers as needed.
      Signed-off-by: NBrent Casavant <bcasavan@sgi.com>
      Acked-by: NPat Gefre <pfg@sgi.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      d4c477ca
    • B
      [PATCH] ioc4: CONFIG split · e5d310b3
      Brent Casavant 提交于
      The SGI IOC4 I/O controller chip drivers are currently all configured by
      CONFIG_BLK_DEV_SGIIOC4.  This is undesirable as not all IOC4 hardware features
      are needed by all systems.
      
      This patch adds two configuration variables, CONFIG_SGI_IOC4 for core IOC4
      driver support (see patch 1/3 in this series for further explanation) and
      CONFIG_SERIAL_SGI_IOC4 to independently enable serial port support.
      Signed-off-by: NBrent Casavant <bcasavan@sgi.com>
      Acked-by: NPat Gefre <pfg@sgi.com>
      Acked-by: NJeremy Higdon <jeremy@sgi.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      e5d310b3
    • B
      [PATCH] ioc4: Core driver rewrite · 22329b51
      Brent Casavant 提交于
      This series of patches reworks the configuration and internal structure
      of the SGI IOC4 I/O controller device drivers.
      
      These changes are motivated by several factors:
      
      - The IOC4 chip PCI resources are of mixed use between functions (i.e.
        multiple functions are handled in the same address range, sometimes
        within the same register), muddling resource ownership and initialization
        issues.  Centralizing this ownership in a core driver is desirable.
      
      - The IOC4 chip implements multiple functions (serial, IDE, others not
        yet implemented in the mainline kernel) but is not a multifunction
        PCI device.  In order to properly handle device addition and removal
        as well as module insertion and deletion, an intermediary IOC4-specific
        driver layer is needed to handle these operations cleanly.
      
      - All IOC4 drivers are currently enabled by a single CONFIG value.  As
        not all systems need all IOC4 functions, it is desireable to enable
        these drivers independently.
      
      - The current IOC4 core driver will trigger loading of all function-level
        drivers, as it makes direct calls to them.  This situation should be
        reversed (i.e. function-level drivers cause loading of core driver)
        in order to maintain a clear and least-surprise driver loading model.
      
      - IOC4 hardware design necessitates some driver-level dependency on
        the PCI bus clock speed.  Current code assumes a 66MHz bus, but the
        speed should be autodetected and appropriate compensation taken.
      
      This patch series effects the above changes by a newly and better designed
      IOC4 core driver with which the function-level drivers can register and
      deregister themselves upon module insertion/removal.  By tracking these
      modules, device addition/removal is also handled properly.  PCI resource
      management and ownership issues are centralized in this core driver, and
      IOC4-wide configuration actions such as bus speed detection are also
      handled in this core driver.
      
      This patch:
      
      The SGI IOC4 I/O controller chip implements multiple functions, though it is
      not a multi-function PCI device.  Additionally, various PCI resources of the
      IOC4 are shared by multiple hardware functions, and thus resource ownership by
      driver is not clearly delineated.  Due to the current driver design, all core
      and subordinate drivers must be loaded, or none, which is undesirable if not
      all IOC4 hardware features are being used.
      
      This patch reorganizes the IOC4 drivers so that the core driver provides a
      subdriver registration service.  Through appropriate callbacks the subdrivers
      can now handle device addition and removal, as well as module insertion and
      deletion (though the IOC4 IDE driver requires further work before module
      deletion will work).  The core driver now takes care of allocating PCI
      resources and data which must be shared between subdrivers, to clearly
      delineate module ownership of these items.
      Signed-off-by: NBrent Casavant <bcasavan@sgi.com>
      Acked-by: Pat Gefre <pfg@sgi.com
      Acked-by: NJeremy Higdon <jeremy@sgi.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      22329b51
    • S
      [PATCH] ppc64 iSeries: allow build with no PCI · 145d01e4
      Stephen Rothwell 提交于
      This patch allows iSeries to build with CONFIG_PCI=n.  This is useful for
      partitions that have only virtual I/O.
      Signed-off-by: NStephen Rothwell <sfr@canb.auug.org.au>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      145d01e4
    • M
      [PATCH] cpm_uart: Route SCC2 pins for the STx GP3 board · a1604f91
      Matt Porter 提交于
      Adds SCC2 pin routing specific to the GP3 board.
      Signed-off-by: NMatt Porter <mporter@kernel.crashing.org>
      Signed-off-by: NKumar Gala <kumar.gala@freescale.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      a1604f91
  10. 09 6月, 2005 1 次提交
  11. 05 6月, 2005 1 次提交
  12. 21 5月, 2005 1 次提交
  13. 17 5月, 2005 1 次提交
  14. 12 5月, 2005 1 次提交
  15. 10 5月, 2005 1 次提交
  16. 06 5月, 2005 1 次提交
  17. 01 5月, 2005 7 次提交
  18. 30 4月, 2005 1 次提交
    • S
      [PATCH] ARM: 2654/1: i.MX UART initialization sets and honors UFCR value · 587897f5
      Sascha Hauer 提交于
      Patch from Sascha Hauer
      
      This patch adds UCFR_RFDIV setting into i.MX serial driver.
      This is required, if loader does not fully agree with Linux kernel
      about UART setup manner. Linux only blindly expected some values until
      now. This should enable to use even serial ports not recognized by
      boot-loader as for example third UART found in the bluethoot module.
      Patch also enables to detect original setup baudrate in more cases.
      
      Signed-off-by: Pavel Pisa
      Signed-off-by: Sascha Hauer
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      587897f5
  19. 26 4月, 2005 2 次提交