1. 21 6月, 2019 1 次提交
  2. 15 5月, 2019 2 次提交
  3. 24 4月, 2019 1 次提交
    • R
      ARM: fix function graph tracer and unwinder dependencies · 50362162
      Russell King 提交于
      Naresh Kamboju recently reported that the function-graph tracer crashes
      on ARM. The function-graph tracer assumes that the kernel is built with
      frame pointers.
      
      We explicitly disabled the function-graph tracer when building Thumb2,
      since the Thumb2 ABI doesn't have frame pointers.
      
      We recently changed the way the unwinder method was selected, which
      seems to have made it more likely that we can end up with the function-
      graph tracer enabled but without the kernel built with frame pointers.
      
      Fix up the function graph tracer dependencies so the option is not
      available when we have no possibility of having frame pointers, and
      adjust the dependencies on the unwinder option to hide the non-frame
      pointer unwinder options if the function-graph tracer is enabled.
      Reviewed-by: NMasami Hiramatsu <mhiramat@kernel.org>
      Tested-by: NMasami Hiramatsu <mhiramat@kernel.org>
      Signed-off-by: NRussell King <rmk+kernel@armlinux.org.uk>
      50362162
  4. 23 4月, 2019 2 次提交
  5. 20 4月, 2019 2 次提交
    • L
      ARM: ixp4xx: Convert to SPARSE_IRQ · dc8ef8cd
      Linus Walleij 提交于
      This localizes the <mach/irqs.h> header to the mach-ixp4xx
      directory, removes NR_IRQS and switches IXP4xx over to using
      SPARSE_IRQ.
      
      This is a prerequisite for DT support.
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      dc8ef8cd
    • L
      ARM: ixp4xx: Convert to MULTI_IRQ_HANDLER · 98ac0cc2
      Linus Walleij 提交于
      This rewrites the IXP4xx to use MULTI_IRQ_HANDLER and
      create an irqdomain for the irqchip in the platform. We
      convert the timer to request the interrupt like any other
      driver in the process.
      
      We bump all IRQs to 16+offset to avoid using IRQ 0 and
      set NR_IRQS to 512 (the default for most systems).
      This conveniently fits with the first 16 IRQs being
      pre-allocated when using SPARSE_IRQ.
      
      This is a prerequisite for SPARSE_IRQ and DT boot.
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      98ac0cc2
  6. 17 4月, 2019 1 次提交
  7. 03 4月, 2019 1 次提交
    • W
      locking/rwsem: Remove rwsem-spinlock.c & use rwsem-xadd.c for all archs · 390a0c62
      Waiman Long 提交于
      Currently, we have two different implementation of rwsem:
      
       1) CONFIG_RWSEM_GENERIC_SPINLOCK (rwsem-spinlock.c)
       2) CONFIG_RWSEM_XCHGADD_ALGORITHM (rwsem-xadd.c)
      
      As we are going to use a single generic implementation for rwsem-xadd.c
      and no architecture-specific code will be needed, there is no point
      in keeping two different implementations of rwsem. In most cases, the
      performance of rwsem-spinlock.c will be worse. It also doesn't get all
      the performance tuning and optimizations that had been implemented in
      rwsem-xadd.c over the years.
      
      For simplication, we are going to remove rwsem-spinlock.c and make all
      architectures use a single implementation of rwsem - rwsem-xadd.c.
      
      All references to RWSEM_GENERIC_SPINLOCK and RWSEM_XCHGADD_ALGORITHM
      in the code are removed.
      Suggested-by: NPeter Zijlstra <peterz@infradead.org>
      Signed-off-by: NWaiman Long <longman@redhat.com>
      Signed-off-by: NPeter Zijlstra (Intel) <peterz@infradead.org>
      Acked-by: NLinus Torvalds <torvalds@linux-foundation.org>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: Borislav Petkov <bp@alien8.de>
      Cc: Davidlohr Bueso <dave@stgolabs.net>
      Cc: H. Peter Anvin <hpa@zytor.com>
      Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Tim Chen <tim.c.chen@linux.intel.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: linux-arm-kernel@lists.infradead.org
      Cc: linux-c6x-dev@linux-c6x.org
      Cc: linux-m68k@lists.linux-m68k.org
      Cc: linux-riscv@lists.infradead.org
      Cc: linux-um@lists.infradead.org
      Cc: linux-xtensa@linux-xtensa.org
      Cc: linuxppc-dev@lists.ozlabs.org
      Cc: nios2-dev@lists.rocketboards.org
      Cc: openrisc@lists.librecores.org
      Cc: uclinux-h8-devel@lists.sourceforge.jp
      Link: https://lkml.kernel.org/r/20190322143008.21313-3-longman@redhat.comSigned-off-by: NIngo Molnar <mingo@kernel.org>
      390a0c62
  8. 25 3月, 2019 1 次提交
  9. 01 3月, 2019 1 次提交
  10. 20 2月, 2019 1 次提交
  11. 19 2月, 2019 3 次提交
  12. 14 2月, 2019 3 次提交
  13. 02 2月, 2019 3 次提交
  14. 01 1月, 2019 1 次提交
  15. 21 12月, 2018 1 次提交
  16. 14 12月, 2018 1 次提交
  17. 13 12月, 2018 1 次提交
    • A
      ARM: smp: add support for per-task stack canaries · 189af465
      Ard Biesheuvel 提交于
      On ARM, we currently only change the value of the stack canary when
      switching tasks if the kernel was built for UP. On SMP kernels, this
      is impossible since the stack canary value is obtained via a global
      symbol reference, which means
      a) all running tasks on all CPUs must use the same value
      b) we can only modify the value when no kernel stack frames are live
         on any CPU, which is effectively never.
      
      So instead, use a GCC plugin to add a RTL pass that replaces each
      reference to the address of the __stack_chk_guard symbol with an
      expression that produces the address of the 'stack_canary' field
      that is added to struct thread_info. This way, each task will use
      its own randomized value.
      
      Cc: Russell King <linux@armlinux.org.uk>
      Cc: Kees Cook <keescook@chromium.org>
      Cc: Emese Revfy <re.emese@gmail.com>
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: Laura Abbott <labbott@redhat.com>
      Cc: kernel-hardening@lists.openwall.com
      Acked-by: NNicolas Pitre <nico@linaro.org>
      Signed-off-by: NArd Biesheuvel <ard.biesheuvel@linaro.org>
      Signed-off-by: NKees Cook <keescook@chromium.org>
      189af465
  18. 06 12月, 2018 1 次提交
  19. 02 12月, 2018 1 次提交
  20. 23 11月, 2018 5 次提交
  21. 08 11月, 2018 2 次提交
  22. 31 10月, 2018 2 次提交
  23. 28 9月, 2018 1 次提交
  24. 03 8月, 2018 1 次提交
    • P
      ARM: Convert to GENERIC_IRQ_MULTI_HANDLER · 4c301f9b
      Palmer Dabbelt 提交于
      Converts the ARM interrupt code to use the recently added
      GENERIC_IRQ_MULTI_HANDLER, which is essentially just a copy of ARM's
      existhing MULTI_IRQ_HANDLER.  The only changes are:
      
      * handle_arch_irq is now defined in a generic C file instead of an
        arm-specific assembly file.
       
      * handle_arch_irq is now marked as __ro_after_init.
      Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Cc: linux@armlinux.org.uk
      Cc: catalin.marinas@arm.com
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: jonas@southpole.se
      Cc: stefan.kristiansson@saunalahti.fi
      Cc: shorne@gmail.com
      Cc: jason@lakedaemon.net
      Cc: marc.zyngier@arm.com
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: nicolas.pitre@linaro.org
      Cc: vladimir.murzin@arm.com
      Cc: keescook@chromium.org
      Cc: jinb.park7@gmail.com
      Cc: yamada.masahiro@socionext.com
      Cc: alexandre.belloni@bootlin.com
      Cc: pombredanne@nexb.com
      Cc: Greg KH <gregkh@linuxfoundation.org>
      Cc: kstewart@linuxfoundation.org
      Cc: jhogan@kernel.org
      Cc: mark.rutland@arm.com
      Cc: ard.biesheuvel@linaro.org
      Cc: james.morse@arm.com
      Cc: linux-arm-kernel@lists.infradead.org
      Cc: openrisc@lists.librecores.org
      Link: https://lkml.kernel.org/r/20180622170126.6308-3-palmer@sifive.com
      4c301f9b
  25. 02 8月, 2018 1 次提交