The pins for i2c5 can either be configured as "I2C5" which means that
they're controlled by the normal RK3288 I2C controller or as "EDP / HDMI
I2C".  It's unclear why EDP is referenced here since apparently setting
the mux to this position enables I2C communication using the dw_hdmi
block with a patch like <https://patchwork.kernel.org/patch/7098101/>.

There appear to be some reasons why using the builtin I2C controller in
dw_hdmi is better than using the normal RK3288 I2C controller, so boards
based on rk3288 might eventually want to use this pinmux if it's known
to work.

Once driver support in dw_hdmi lands, boards would use this by selecting
this pinctrl for the HDMI block and then _not_ specifying a ddc-i2c-bus
and _not_ setting the status to "okay" for i2c5 (which uses the same
pins).
Signed-off-by: NDouglas Anderson <dianders@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The flow control lines from a user accessible UART are optional,
the user might not have anything connected to those pins.
In order to prevent random interrupts happening and noise affecting
the cts pin should be pulled up.

Note that the default state for that pin on the rk3288 is pulled up,
so this patch merely restores them.

This is similar to what we're already doing with the RX pin,
so it should be safe. At worst it might be a slightly higher power usage
(through ~50 kohms) when the cts is low.
Suggested-by: NNeil Hendin <nhendin@chromium.org>
Signed-off-by: NAlexandru M Stan <amstan@chromium.org>
Reviewed-by: NDouglas Anderson <dianders@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The all current Rockchip SoCs supporting 4GB of ram have problems accessing
the memory region 0xfe000000~0xff000000. This also seems to includes the
rk3368 arm64 soc.

All current code handling dma memory oddities I could find, seem to involve
soc-specific code (zone-dma or so) while this issue is shared between arm32
and arm64 socs from Rockchip, which would need to have this described in
the soc devicetree on both socs.

Limiting the dma-zone alone also does not solve the issue and as the
dma-masks need to be a power-of-two in the kernel, the next lower dma-mask
brings memory usable for dma down to 2GB.

So as a stop-gap block off the affected region to prevent its use by
devices with 4GB of memory, like some recent Chromebooks.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NDouglas Anderson <dianders@chromium.org>

The rk3288 uses spi irqs for the arm-pmu on individual cpu cores, so needs
the affinity to them defined.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NSonny Rao <sonnyrao@chromium.org>

The watchdog irq is actually SPI 79, which translates to the original
111 in the manual where the SPI irqs start at 32.
The current dw_wdt driver does not use the irq at all, so this issue
never surfaced. Nevertheless fix this for a time we want to use the irq.

Fixes: 2ab557b7 ("ARM: dts: rockchip: add core rk3288 dtsi")
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NDouglas Anderson <dianders@chromium.org>

Which fixes warning "no reset control found" by the same time
Signed-off-by: NRomain Perier <romain.perier@gmail.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

GPLv2-only devicetrees make reuse difficult for software components licensed
under a different license.

The consensus is that a GPL/X11 dual-license should allow all necessary uses,
so relicense the rk3288.dtsi to this combination.

CCs were aquired by git shortlog -sne so it should've hopefully catched
every contributor.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Acked-by: NDoug Anderson <dianders@chromium.org>
Acked-by: NSonny Rao <sonnyrao@chromium.org>
Acked-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: NKever Yang <kever.yang@rock-chips.com>
Acked-by: NCaesar Wang <caesar.wang@rock-chips.com>
Acked-by: NLin Huang <hl@rock-chips.com>
Acked-by: NChris Zhong <zyw@rock-chips.com>
Acked-by: Jianqun Xu<jay.xu@rock-chips.com>
Acked-by: NDaniel Kurtz <djkurtz@chromium.org>
Acked-by: NRoger Chen <roger.chen@rock-chips.com>
Acked-by: NYunzhi Li <lyz@rock-chips.com>

on behalf of Rockchip
Acked-by: NEddie Cai <eddie.cai@rock-chips.com>

Add properties for dwc2 usb device controller according to
Documentation/devicetree/bindings/usb/dwc2.txt
Signed-off-by: NYunzhi Li <lyz@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This adds the dts node for the PMU with the correct PMUIRQ interrupts
for each core.
Signed-off-by: NSonny Rao <sonnyrao@chromium.org>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This block should not be enabled by default or else if the kconfig is set,
it will try to load/probe even if there's no phy connected.
Signed-off-by: NAlexandru M Stan <amstan@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This patch adds a device_node for RK3288 SoC usb phy. It also
defines the phy to be used by three usb controllers: usb_host0/1
and usb_otg.
Signed-off-by: NYunzhi Li <lyz@rock-chips.com>
Tested-by: NDoug Anderson <dianders@chromium.org>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Currently the hdmi driver is using one of the soc i2c busses for ddc probing
and while documentation always specifies i2c5 as hdmi-i2c it could very well
be any other bus as well.

Therefore this is a property of the board and should be specified there.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add the clock property for the watchdog on rk3288 socs.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Tested-by: NDoug Anderson <dianders@chromium.org>

The rk3288 board uses the architected timers and these ones are shutdown when
the cpu is powered down. There is a need of a broadcast timer in this case to
ensure proper wakeup when the cpus are in sleep mode and a timer expires.

Add the timer node for the broadcast timer.
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add an hdmi node, and also add hdmi endpoints to vopb and vopl
output port nodes.
Signed-off-by: NAndy Yan <andy.yan@rock-chips.com>
Signed-off-by: NYakir Yang <ykk@rock-chips.com>
Reviewed-by: NDaniel Kurtz <djkurtz@chromium.org>
Tested-by: NDaniel Kurtz <djkurtz@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add devicetree nodes for rk3288 VOP (Video Output Processors), and the
top level display-subsystem root node.

Later patches add endpoints (eDP, HDMI, LVDS, etc) that attach to the
VOPs' output ports.
Signed-off-by: NDaniel Kurtz <djkurtz@chromium.org>
Signed-off-by: NMark yao <mark.yao@rock-chips.com>
Reviewed-by: NStephane Marchesin <marcheu@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

add gmac info in rk3288.dtsi for GMAC driver

changes since v2:
1. add drive-strength in the pinctrl settings
Signed-off-by: NRoger Chen <roger.chen@rock-chips.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

add pmu sram node for suspend, add global_pwroff pinctrl.
The pmu sram is used to store the resume code.
global_pwroff is held low level at work, it would be pull to high
when entering suspend. reference this in the board DTS file since
some boards need it.
Signed-off-by: NTony Xie <xxx@rock-chips.com>
Signed-off-by: NChris Zhong <zyw@rock-chips.com>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Tested-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

All of mmc controllers include SDMMC, SDIO0, SDIO1, and EMMC on RK3288
are limited to 150Mhz. It was mainly caused by two reasons:
- RK3288's IO pad(except DDR IO pad) is generic, which can only support
  the max of 150Mhz.
- Mmc controller was designed at 150Mhz, and the pressure test by IC team
  was based on this freequency point.
Signed-off-by: NAddy Ke <addy.ke@rock-chips.com>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Tested-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This will enable use of physical arch timers on rk3288, where each
core comes out of reset with a different virtual offset.  Using
physical timers will help with SMP booting on coreboot and older
u-boot and should also allow suspend-resume and cpu-hotplug to work on
all firmwares.

Firmware which does initialize the cpu registers properly at boot and
cpu-hotplug can remove this property from the device tree.
Signed-off-by: NSonny Rao <sonnyrao@chromium.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

We now have the physical-timers patches lined up as a dependency in this same
branch, so we can revert the temporary disablement.

This reverts commit b77d4394.
Signed-off-by: NOlof Johansson <olof@lixom.net>

If for some reason we are unable to shut it down in orderly fashion
(kernel is stuck holding a lock or similar), then hardware TSHUT will
reset it.

If the temperature is over 95C over a period of time the thermal shutdown
of the tsadc is invoked with can either reset the entire chip via the CRU,
or notify the PMIC via a GPIO. This should be set in the specific board.
Signed-off-by: NCaesar Wang <caesar.wang@rock-chips.com>
Reviewed-by: NDmitry Torokhov <dmitry.torokhov@gmail.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Stock firmware on rk3288 does not initizalize the CNTVOFF registers
of the architected timer correctly. This introduces issues with the
newly added SMP support for rk3288, resulting in rcu stalls due to
differing timer values per core.

There exist preliminary and tested patches for u-boot for this problem,
but there are a minority of boards using other bootloaders like coreboot.

There also is currently a second solution for miss-initialized architected
timers in the works:
- clocksource: arch_timer: Fix code to use physical timers when requested
- clocksource: arch_timer: Allow the device tree to specify uninitialized timer registers

Therefore disable smp on rk3288 again till these are finalized, also
allowing coreboot-based boards to boot again.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add device nodes for the VOP iommus.
Device nodes for other iommus will be added in later patches.

The iommu nodes use the #iommu-cells property as described in:
  Documentation/devicetree/bindings/iommu/iommu.txt
Signed-off-by: NDaniel Kurtz <djkurtz@chromium.org>
Signed-off-by: NSimon Xue <xxm@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This patch add reset for CPU nodes to use the reset controller.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Tested-by: NKevin Hilman <khilman@linaro.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This patch add intmem node des which is needed by platsmp.c
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Tested-by: NKevin Hilman <khilman@linaro.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This patch add pmu reference and enable-method for smp
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Tested-by: NKevin Hilman <khilman@linaro.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Now that SPI DMA has been fixed on rk3288 we can enable it.
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NAlexandru M Stan <amstan@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

We need to initialize PLL rate and some of bus clock rate while
kernel init, for there is no other module will do that.

Basically on rk3288 we use GPLL for cpu bus, peripheral bus and
most of peripheral clock, CPLL for devices who require 50M/200M
clock rate, leave NPLL behind for special requirement from
display system.

The common-clock-framework will help us to select best source for
child clocks after we init the PLLs propriety.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Tested-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add basic OPP entries for current supported Rockchip SoCs.
The operating points are currently very conservative, so individual
boards may opt to redefine them.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

Add dt for rk3288 i2s controller, since i2s clock pins and data pins
default to be GPIO, this patch also add pinctrl to mux them.

Tested on RK3288 board.
Signed-off-by: NJianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

It's convenient (and less confusing to people reading logs) if the
eMMC port on rk3288 is consistenly marked with mmc0 and the sdmmc port
on rk3288 is consistently marked with mmc1.  Add the appropriate
aliases.
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Reviewed-by: NSonny Rao <sonnyrao@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This adds basic SPI nodes to the base rk3288 device tree file.

A few notes:
* It's assumed that most users of the SPI ports are using chip select
  0.  Thus the default pinctrl for the ports enables chip select 0
  (but not chip select 1 on ports that have it).  If a board wants to
  use chip select 1 or wants a GPIO chip select the board should
  override the pinctrl (just like boards can override UART pinctrl if
  they have hardware flow control).
* Since SPI DMA support appears broken and the SPI works fine without
  DMA we don't include the DMA references.  That can come in a later
  change.
Signed-off-by: Nhuang lin <hl@rock-chips.com>
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

rk3288 has two kind of usb controller, this add the dwc2 controller
for otg and host1.

Controller can works with usb PHY default setting and Vbus on.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Tested-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This patch requires that <https://patchwork.kernel.org/patch/4701721/>
land in order to compile.
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NAddy Ke <addy.ke@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add both the bus and peripheral pl330 dma controllers present in rk3288 socs.
The first dma controller can change between secure and non-secure mode. Both
instances are added but the non-secure variant is left disabled by default,
as on the majority of boards the bootloader leaves it in secure mode.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Tested-by: NKever Yang <kever.yang@rock-chips.com>

Add the core device nodes for the SARADC found on both the Cortex-A9 series
(rk3066 and rk3188) as well as the newer rk3288.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This adds the PWM info (other than the VOP PWM) to the main rk3288
dtsi file.
Signed-off-by: NCaesar Wang <caesar.wang@rock-chips.com>
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This adds support for the sdmmc and emmc ports on the rk3288.
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The EHCI and HSIC device tree nodes were added in the wrong place.
Fix them.
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NOlof Johansson <olof@lixom.net>