1. 07 8月, 2013 2 次提交
  2. 20 7月, 2013 1 次提交
  3. 13 7月, 2013 1 次提交
    • D
      drm/i915: fix pfit regression for non-autoscaled resolutions · 21d8a475
      Daniel Vetter 提交于
      I.e. for letter/pillarboxing. For those cases we need to adjust the
      mode a bit, but Jesse gmch pfit refactoring in
      
      commit 2dd24552
      Author: Jesse Barnes <jbarnes@virtuousgeek.org>
      Date:   Thu Apr 25 12:55:01 2013 -0700
      
          drm/i915: factor out GMCH panel fitting code and use for eDP v3
      
      broke that by reordering the computation of the gmch pfit state with
      the block of code that prepared the adjusted mode for it and told the
      modeset core not to overwrite the adjusted mode with default settings.
      
      We might want to switch around the core code to just fill in defaults,
      but this code predates the pipe_config modeset rework. And in the old
      crtc helpers we did not have a suitable spot to do this.
      
      Cc: Mika Kuoppala <mika.kuoppala@intel.com>
      Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
      Cc: Hans de Bruin <jmdebruin@xmsnet.nl>
      Reported-and-tested-by: NHans de Bruin <jmdebruin@xmsnet.nl>
      Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      21d8a475
  4. 23 5月, 2013 1 次提交
  5. 30 4月, 2013 2 次提交
  6. 26 4月, 2013 3 次提交
  7. 25 4月, 2013 3 次提交
  8. 18 4月, 2013 1 次提交
  9. 02 4月, 2013 1 次提交
  10. 28 3月, 2013 2 次提交
  11. 24 3月, 2013 1 次提交
  12. 23 3月, 2013 1 次提交
  13. 15 2月, 2013 1 次提交
  14. 05 12月, 2012 1 次提交
  15. 22 11月, 2012 1 次提交
    • D
      drm/i915: resurrect panel lid handling · a726915c
      Daniel Vetter 提交于
      But disabled by default. This essentially reverts
      
      commit bcd5023c
      Author: Dave Airlie <airlied@redhat.com>
      Date:   Mon Mar 14 14:17:55 2011 +1000
      
          drm/i915: disable opregion lid detection for now
      
      but leaves the autodetect mode disabled. There's also the explicit lid
      status option added in
      
      commit fca87409
      Author: Chris Wilson <chris@chris-wilson.co.uk>
      Date:   Thu Feb 17 13:44:48 2011 +0000
      
          drm/i915: Add a module parameter to ignore lid status
      
      Which overloaded the meaning for the panel_ignore_lid parameter even
      more. To fix up this mess, give the non-negative numbers 0,1 the
      original meaning back and use negative numbers to force a given state.
      So now we have
      
      1  - disable autodetect, return unknown
      0  - enable autodetect
      -1 - force to disconnected/lid closed
      -2 - force to connected/lid open
      
      v2: My C programmer license has been revoked ...
      
      v3: Beautify the code a bit, as suggested by Chris Wilson.
      
      Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=27622Tested-by: NAndreas Sturmlechner <andreas.sturmlechner@gmail.com>
      Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      a726915c
  16. 12 11月, 2012 1 次提交
  17. 26 10月, 2012 1 次提交
  18. 23 10月, 2012 3 次提交
  19. 04 9月, 2012 1 次提交
  20. 12 8月, 2012 1 次提交
  21. 06 8月, 2012 1 次提交
  22. 20 7月, 2012 1 次提交
    • P
      drm/i915: don't forget the PCH backlight registers · a4f32fc3
      Paulo Zanoni 提交于
      When we enable/disable the CPU backlight registers we can't forget to
      enable/disable the PCH backlight registers. Since we're using the CPU
      registers we should also unset the override bit.
      
      Fixes a regression on the following commit:
        drm/i915: properly enable the blc controller on the right pipe
      
      The commit just deleted the code that sets the PCH registers, so it
      was relying on the values set by the BIOS. I told my BIOS to boot on
      the DVI monitor instead of the LVDS panel, so I noticed the bug.
      Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      a4f32fc3
  23. 13 6月, 2012 1 次提交
    • D
      drm/i915: properly enable the blc controller on the right pipe · 24ded204
      Daniel Vetter 提交于
      On gen4+ we have a bitfield to specify from which pipe the backlight
      controller should take it's clock. For PCH split platforms we've
      already set these up, but only at initialization time. And without
      taking into account the 3rd pipe added with ivb.
      
      For gen4, we've completely ignored these. Although we do restrict lvds
      to the 2nd pipe, so this is only a problem on machines where we boot
      up with the lvds on the first pipe.
      
      So restructure the code to enable the backlight on the right pipe at
      modeset time.
      
      v2: For odd reasons panel_enable_backlight gets called twice in a
      modeset, so we can't WARN_ON in there if the backlight controller is
      switched on already.
      
      v3: backlight enable can also be called through dpms on, so the check
      in there is legit. Update the comment to reflect that.
      Tested-By: NKamal Mostafa <kamal@canonical.com>
      Bugzilla: https://bugs.launchpad.net/bugs/954661
      Cc: Carsten Emde <C.Emde@osadl.org>
      Reviewed-by: NEugeni Dodonov <eugeni.dodonov@intel.com>
      Signed-Off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      24ded204
  24. 05 6月, 2012 1 次提交
  25. 22 5月, 2012 1 次提交
  26. 16 4月, 2012 1 次提交
  27. 19 3月, 2012 3 次提交
  28. 11 2月, 2012 1 次提交
    • D
      drm/i915: fixup interlaced vertical timings confusion, part 1 · ca9bfa7e
      Daniel Vetter 提交于
      We have a pretty decent confusion about vertical timings of interlaced
      modes. Peter Ross has written a patch that makes interlace modes work
      on a lot more platforms/output combinations by doubling the vertical
      timings.
      
      The issue with that patch is that core drm _does_ support specifying
      whether we want these vertical timings in fields or frames, we just
      haven't managed to consistently use this facility. The relavant
      function is drm_mode_set_crtcinfo, which fills in the crtc timing
      information.
      
      The first thing to note is that the drm core keeps interlaced modes in
      frames, but displays modelines in fields. So when the crtc modeset
      helper copies over the mode into adjusted_mode it will already contain
      vertical timings in half-frames. The result is that the fixup code in
      intel_crtc_mode_fixup doesn't actually do anything (in most cases at
      least).
      
      Now gen3+ natively supports interlaced modes and wants the vertical
      timings in frames. Which is what sdvo already fixes up, at least under
      some conditions.
      
      There are a few other place that demand vertical timings in fields
      but never actually deal with interlaced modes, so use frame timings
      for consistency, too. These are:
      - lvds panel,
      - dvo encoders - dvo is the only way gen2 could support interlaced
        mode, but currently we don't support any encoders that do.
      - tv out - despite that the tv dac sends out an interlaced signal it
        expects a progressive mode pipe configuration.
      All these encoders enforce progressive modes by resetting
      interlace_allowed.
      
      Hence we always want crtc vertical timings in frames. Enforce this in
      our crtc mode_fixup function and rip out any redudant timing
      computations from the encoders' mode_fixup function.
      
      v2-4: Adjust the vertical timings a bit.
      
      v5: Split out the 'subtract-one for interlaced' fixes.
      
      v6: Clarify issues around tv-out and gen2.
      Reviewed-by: NEugeni Dodonov <eugeni.dodonov@intel.com>
      Reviewed-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
      Tested-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
      Tested-by: NChristopher Egert <cme3000@gmail.com>
      Tested-by: NAlfonso Fiore <alfonso.fiore@gmail.com>
      Signed-Off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      ca9bfa7e
  29. 17 1月, 2012 1 次提交