1. 22 8月, 2013 8 次提交
  2. 12 6月, 2013 1 次提交
  3. 08 3月, 2013 2 次提交
    • B
      sfc: Enable RX DMA scattering where possible · 85740cdf
      Ben Hutchings 提交于
      Enable RX DMA scattering iff an RX buffer large enough for the current
      MTU will not fit into a single page and the NIC supports DMA
      scattering for kernel-mode RX queues.
      
      On Falcon and Siena, the RX_USR_BUF_SIZE field is used as the DMA
      limit for both all RX queues with scatter enabled.  Set it to 1824,
      matching what Onload uses now.
      
      Maintain a statistic for frames truncated due to lack of descriptors
      (rx_nodesc_trunc).  This is distinct from rx_frm_trunc which may be
      incremented when scattering is disabled and implies an over-length
      frame.
      
      Whenever an MTU change causes scattering to be turned on or off,
      update filters that point to the PF queues, but leave others
      unchanged, as VF drivers assume scattering is off.
      
      Add n_frags parameters to various functions, and make them iterate:
      - efx_rx_packet()
      - efx_recycle_rx_buffers()
      - efx_rx_mk_skb()
      - efx_rx_deliver()
      
      Make efx_handle_rx_event() responsible for updating
      efx_rx_queue::removed_count.
      
      Change the RX pipeline state to a starting ring index and number of
      fragments, and make __efx_rx_packet() responsible for clearing it.
      
      Based on earlier versions by David Riddoch and Jon Cooper.
      Signed-off-by: NBen Hutchings <bhutchings@solarflare.com>
      85740cdf
    • A
      sfc: Add AER and EEH support for Siena · 626950db
      Alexandre Rames 提交于
      The Linux side of EEH is triggered by MMIO reads, but this
      driver's data path does not issue any MMIO reads (except in
      legacy interrupt mode).  Therefore add a monitor function
      to poll EEH periodically.
      
      When preparing to reset the device based on our own error
      detection, also poll EEH and defer to its recovery mechanism
      if appropriate.
      
      [bwh: Use a separate condition for the initial link poll; fix some
       style errors]
      Signed-off-by: NBen Hutchings <bhutchings@solarflare.com>
      626950db
  4. 01 12月, 2012 2 次提交
  5. 19 9月, 2012 1 次提交
  6. 17 7月, 2012 2 次提交
    • B
      sfc: Fix interface statistics running backward · b7f514af
      Ben Hutchings 提交于
      Some interface statistics are computed in such a way that they can
      sometimes decrease (and even underflow).  Since the computed value
      will never be greater than the true value, we fix this by only storing
      the computed value when it increases.
      Signed-off-by: NBen Hutchings <bhutchings@solarflare.com>
      b7f514af
    • B
      sfc: Disable VF queues during register self-test · d4f2cecc
      Ben Hutchings 提交于
      Currently VF queues and drivers may remain active during this test.
      This could cause memory corruption or spurious test failures.
      Therefore we reset the port/function before running these tests on
      Siena.
      
      On Falcon this doesn't work: we have to do some additional
      initialisation before some blocks will work again.  So refactor the
      reset/register-test sequence into an efx_nic_type method so
      efx_selftest() doesn't have to consider such quirks.
      
      In the process, fix another minor bug: Siena does not have an
      'invisible' reset and the self-test currently fails to push the PHY
      configuration after resetting.  Passing RESET_TYPE_ALL to
      efx_reset_{down,up}() fixes this.
      Signed-off-by: NBen Hutchings <bhutchings@solarflare.com>
      d4f2cecc
  7. 07 3月, 2012 1 次提交
  8. 16 2月, 2012 2 次提交
    • B
      sfc: Add SR-IOV back-end support for SFC9000 family · cd2d5b52
      Ben Hutchings 提交于
      On the SFC9000 family, each port has 1024 Virtual Interfaces (VIs),
      each with an RX queue, a TX queue, an event queue and a mailbox
      register.  These may be assigned to up to 127 SR-IOV virtual functions
      per port, with up to 64 VIs per VF.
      
      We allocate an extra channel (IRQ and event queue only) to receive
      requests from VF drivers.
      
      There is a per-port limit of 4 concurrent RX queue flushes, and queue
      flushes may be initiated by the MC in response to a Function Level
      Reset (FLR) of a VF.  Therefore, when SR-IOV is in use, we submit all
      flush requests via the MC.
      
      The RSS indirection table is shared with VFs, so the number of RX
      queues used in the PF is limited to the number of VIs per VF.
      
      This is almost entirely the work of Steve Hodgson, formerly
      shodgson@solarflare.com.
      Signed-off-by: NBen Hutchings <bhutchings@solarflare.com>
      cd2d5b52
    • B
      sfc: Allocate SRAM between buffer table and descriptor caches at init time · 28e47c49
      Ben Hutchings 提交于
      Each port has a block of 64-bit SRAM that is divided between buffer
      table and descriptor cache regions at initialisation time.  Currently
      we use a fixed allocation, but it needs to be changed to support
      larger numbers of queues.
      Signed-off-by: NBen Hutchings <bhutchings@solarflare.com>
      28e47c49
  9. 27 1月, 2012 5 次提交
    • B
      sfc: Add hwmon driver for boards using SFC9000-family controllers · 55c5e0f8
      Ben Hutchings 提交于
      The SFC9000-family controllers have firmware to manage all board
      peripherals including temperature, heat sink continuity and voltage
      sensors.  The firmware reports sensor alarms, which we log, and
      will shut down the board if necessary.
      
      Some users may want to monitor their boards more closely, so add an
      hwmon driver that exposes all sensors reported by the firmware.  Move
      efx_mcdi_sensor_event() into the new file so it can share the array of
      sensor labels with the hwmon driver.
      Signed-off-by: NBen Hutchings <bhutchings@solarflare.com>
      55c5e0f8
    • B
      sfc: Correct interrupt timer quantum for Siena (normal and turbo mode) · cc180b69
      Ben Hutchings 提交于
      We currently assume that the timer quantum for Siena is 5 us, the same
      as for Falcon.  This is not correct; timer ticks are generated on a
      rota which takes a minimum of 768 cycles (each event delivery or other
      timer change will delay it by 3 cycles).  The timer quantum should be
      6.144 or 3.072 us depending on whether turbo mode is active.
      
      Replace EFX_IRQ_MOD_RESOLUTION with a timer_quantum_ns field in struct
      efx_nic, initialised by the efx_nic_type::probe function.
      
      While we're at it, replace EFX_IRQ_MOD_MAX with a timer_period_max
      field in struct efx_nic_type.
      Signed-off-by: NBen Hutchings <bhutchings@solarflare.com>
      cc180b69
    • M
    • B
      sfc: Remove efx_nic_type::push_multicast_hash operation · 30b81cda
      Ben Hutchings 提交于
      Both implementations of efx_nic_type::reconfigure_mac operation
      push the multicast hash filter to the hardware.  It is therefore
      redundant to call efx_nic_type::push_multicast_hash as well.
      
      efx_mcdi_mac_reconfigure() also uses this operation, but the
      implementation for Siena just uses MCDI anyway.  Merge that into
      efx_mcdi_mac_reconfigure().
      Signed-off-by: NBen Hutchings <bhutchings@solarflare.com>
      30b81cda
    • B
      sfc: Merge efx_mac_operations into efx_nic_type · 710b208d
      Ben Hutchings 提交于
      No NICs need to switch efx_mac_operations at run-time, and the MAC
      operations are fairly closely bound to NIC types.
      
      Move efx_mac_operations::reconfigure to efx_nic_type::reconfigure_mac
      and efx_mac_operations::check_fault fo efx_nic_type::check_mac_fault.
      Change callers to call through efx->type or directly if the NIC type
      is known.
      
      Remove efx_mac_operations::update_stats.  The implementations for
      Falcon used to fetch MAC statistics synchronously and this was used by
      efx_register_netdev() to clear statistics after running self-tests.
      However, it now only converts statistics that have already been
      fetched (and that only for Falcon), and the call from
      efx_register_netdev() has no effect.
      Signed-off-by: NBen Hutchings <bhutchings@solarflare.com>
      710b208d
  10. 20 12月, 2011 1 次提交
  11. 17 9月, 2011 1 次提交
  12. 11 8月, 2011 1 次提交
  13. 25 6月, 2011 2 次提交
    • S
      sfc: Fix Siena mac statistics on big endian platforms · a659b2a9
      Steve Hodgson 提交于
      [bwh: Use __force in the one place it's needed]
      Signed-off-by: NBen Hutchings <bhutchings@solarflare.com>
      a659b2a9
    • B
      sfc: Fix mapping of reset reasons and flags to methods · 0e2a9c7c
      Ben Hutchings 提交于
      There are certain hardware bugs that may occur on Falcon during normal
      operation, that require a reset to recover from.  We try to minimise
      disruption by keeping the PHY running, following a reset sequence
      labelled as 'invisible'.
      
      Siena does not suffer from these hardware bugs, so we have not
      implemented an 'invisible' reset sequence.  However, if a similar
      error does occur (due to a hardware fault or software bug) then the
      code shared with Falcon will wrongly assume that the PHY is not being
      reset.
      
      Since the mapping of reset reasons (internal) and flags (ethtool) to
      methods must differ significantly between NIC types, move it into
      per-NIC-type functions (replacing the insufficient reset_world_flags
      field).
      Signed-off-by: NBen Hutchings <bhutchings@solarflare.com>
      0e2a9c7c
  14. 22 6月, 2011 1 次提交
  15. 12 5月, 2011 1 次提交
    • B
      sfc: Always map MCDI shared memory as uncacheable · 747df225
      Ben Hutchings 提交于
      We enabled write-combining for memory-mapped registers in commit
      65f0b417, but inhibited it for the
      MCDI shared memory where this is not supported.  However,
      write-combining mappings also allow read-reordering, which may also
      be a problem.
      
      I found that when an SFC9000-family controller is connected to an
      Intel 3000 chipset, and write-combining is enabled, the controller
      stops responding to PCIe read requests during driver initialisation
      while the driver is polling for completion of an MCDI command.  This
      results in an NMI and system hang.  Adding read memory barriers
      between all reads to the shared memory area appears to reduce but not
      eliminate the probability of this.
      
      We have not yet established whether this is a bug in our BIU or in the
      PCIe bridge.  For now, work around by mapping the shared memory area
      separately.
      Signed-off-by: NBen Hutchings <bhutchings@solarflare.com>
      747df225
  16. 15 4月, 2011 1 次提交
  17. 01 3月, 2011 3 次提交
  18. 04 12月, 2010 2 次提交
  19. 21 10月, 2010 1 次提交
  20. 22 9月, 2010 1 次提交
  21. 11 9月, 2010 1 次提交