- 25 2月, 2011 11 次提交
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由 Ben Skeggs 提交于
We may well be making more use of semaphores in the future, having the entire VM available makes requiring DMA objects for each and every semaphore block unnecessary. Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
Evil, evil chipset. Worst of both worlds. Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
And also, don't disable PFIFO IRQs completely whenever we recieve one, just when we don't know about it already. Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
These are the same semaphores nvc0 will use, and they potentially allow us to do much cooler things than our current inter-channel sync impl. Lets switch to them where possible now for some testing. Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
v2. moved nv44 pciegart table back to instmem, where it's not accessible by userspace clients. Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
In preparation for the addition of a new nv40 backend, we'll need to be able to distinguish between a paged dma object and the on-chip GART. Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
In preparation for the addition of a new nv40 pcie backend. Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
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- 23 2月, 2011 21 次提交
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由 Dave Airlie 提交于
This reverts commit 5a893fc2. This causes a use after free in the ttm free alloc pages path, when it tries to get the be after the be has been destroyed. Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Dave Airlie 提交于
* drm-mm-cleanup: radeon: move blit functions to radeon_asic.h radeon: kill decls for inline functions radeon: consolidate asic-specific function decls for r600 & later drm/radeon: kill radeon_bo->gobj pointer drm/radeon: introduce gem_to_radeon_bo helper drm/radeon: embed struct drm_gem_object drm: mm: add helper to unwind scan state drm: mm: add api for embedding struct drm_mm_node drm: mm: extract node insert helper functions drm: mm: track free areas implicitly drm/nouveau: don't munge in drm_mm internals
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由 Dave Airlie 提交于
Merge branch 'stable/ttm.pci-api.v5' of git://git.kernel.org/pub/scm/linux/kernel/git/konrad/xen into drm-next * 'stable/ttm.pci-api.v5' of git://git.kernel.org/pub/scm/linux/kernel/git/konrad/xen: ttm: Include the 'struct dev' when using the DMA API. nouveau/ttm/PCIe: Use dma_addr if TTM has set it. radeon/ttm/PCIe: Use dma_addr if TTM has set it. ttm: Expand (*populate) to support an array of DMA addresses. ttm: Utilize the DMA API for pages that have TTM_PAGE_FLAG_DMA32 set. ttm: Introduce a placeholder for DMA (bus) addresses.
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由 Chris Wilson 提交于
Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Chris Wilson 提交于
Using an order 19 drm_ht for the mmap offsets is a little obscene. That means that will a fully populated GTT with every single object mmaped at least once in its lifetime, there will be exactly one object in each bucket. Typically systems only have at most a few thousand objects, though you may see a KDE desktop hit 50000. And most of those should never be mapped... On my systems, just using an order 10 ht would still have an average occupancy less than 1, so apply a small safety factor and use an order 12 ht, like the other mmap offset ht. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Chris Wilson 提交于
... and fixup some methods to accept the constant argument. Now that constant module arrays are loaded into read-only memory, using const appropriately has some benefits beyond warning the programmer about likely mistakes. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Dave Airlie 提交于
the texture checking code didn't work for block formats like s3tc, this overhauls it to work for all types. v2: add texture array support. v3: add subsampled formats Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Ben Skeggs 提交于
Nouveau doesn't have enough information at ttm_backend_func.bind() time to implement things like tiled GART, or to keep a buffer at a constant address in the GPU virtual address space no matter where in physical memory it's placed. To resolve this, nouveau will handle binding of all buffers to the GPU itself from the move_notify() hook. This commit ensures it's called for all buffer moves. Talked to Dave about the impact on radeon, which uses move_notify, it doesn't look like anything should break there. Signed-off-by: NBen Skeggs <bskeggs@redhat.com> Reviewed-by: NThomas Hellstrom <thomas@shipmail.org> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Rob Clark 提交于
If there is an alpha channel, need to mask in 1's in the alpha channel to prevent the fb from being completely transparent. Signed-off-by: NRob Clark <rob@ti.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Daniel Vetter 提交于
Reviewed-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Daniel Vetter 提交于
Reviewed-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Daniel Vetter 提交于
Now all the asic specific stuff ist mostly hid in radeon_asic.* Reviewed-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Daniel Vetter 提交于
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Daniel Vetter 提交于
... and switch it to container_of upcasting. v2: converted new pageflip code-paths. Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Daniel Vetter 提交于
Unconditionally initialize the drm gem object - it's not worth the trouble not to for the few kernel objects. This patch only changes the place of the drm gem object, access is still done via pointers. v2: Uncoditionally align the size in radeon_bo_create. At least the r600/evergreen blit code didn't to this, angering the paranoid gem code. Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Daniel Vetter 提交于
With the switch to implicit free space accounting one pointer got unused when scanning. Use it to create a single-linked list to ensure correct unwinding of the scan state. Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Daniel Vetter 提交于
The old api has a two-step process: First search for a suitable free hole, then allocate from that specific hole. No user used this to do anything clever. So drop it for the embeddable variant of the drm_mm api (the old one retains this ability, for the time being). With struct drm_mm_node embedded, we cannot track allocations anymore by checking for a NULL pointer. So keep track of this and add a small helper drm_mm_node_allocated. Also add a function to move allocations between different struct drm_mm_node. v2: Implement suggestions by Chris Wilson. Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Daniel Vetter 提交于
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Daniel Vetter 提交于
The idea is to track free holes implicitly by marking the allocation immediatly preceeding a hole. To avoid an ugly corner case add a dummy head_node to struct drm_mm to track the hole that spans to complete allocation area when the memory manager is empty. To guarantee that there's always a preceeding/following node (that might be marked as hole_follows == 1), move the mm->node_list list_head to the head_node. The main allocator and fair-lru scan code actually becomes simpler. Only the debug code slightly suffers because free areas are no longer explicit. Also add drm_mm_for_each_node (which will be much more useful when struct drm_mm_node is embeddable). Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Daniel Vetter 提交于
Nouveau was checking drm_mm internals on teardown to see whether the memory manager was initialized. Hide these internals in a small inline helper function. Acked-by: NBen Skeggs <bskeggs@redhat.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Konrad Rzeszutek Wilk 提交于
This makes the accounting when using 'debug_dma_dump_mappings()' and CONFIG_DMA_API_DEBUG=y be assigned to the correct device instead of 'fallback'. No functional change - just cosmetic. Signed-off-by: NKonrad Rzeszutek Wilk <konrad.wilk@oracle.com>
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- 19 2月, 2011 2 次提交
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由 Konrad Rzeszutek Wilk 提交于
If the TTM layer has used the DMA API to setup pages that are TTM_PAGE_FLAG_DMA32 (look at patch titled: "ttm: Utilize the DMA API for pages that have TTM_PAGE_FLAG_DMA32 set"), lets use it when programming the GART in the PCIe type cards. This patch skips doing the pci_map_page (and pci_unmap_page) if there is a DMA addresses passed in for that page. If the dma_address is zero (or DMA_ERROR_CODE), then we continue on with our old behaviour. [v2: Added a review-by tag] Reviewed-by: NThomas Hellstrom <thomas@shipmail.org> Signed-off-by: NKonrad Rzeszutek Wilk <konrad.wilk@oracle.com> Tested-by: NIan Campbell <ian.campbell@citrix.com>
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由 Konrad Rzeszutek Wilk 提交于
If the TTM layer has used the DMA API to setup pages that are TTM_PAGE_FLAG_DMA32 (look at patch titled: "ttm: Utilize the dma_addr_t array for pages that are to in DMA32 pool."), lets use it when programming the GART in the PCIe type cards. This patch skips doing the pci_map_page (and pci_unmap_page) if there is a DMA addresses passed in for that page. If the dma_address is zero (or DMA_ERROR_CODE), then we continue on with our old behaviour. [v2: Fixed an indentation problem, added reviewed-by tag] [v3: Added Acked-by Jerome] Acked-by: NJerome Glisse <j.glisse@gmail.com> Reviewed-by: NThomas Hellstrom <thomas@shipmail.org> Signed-off-by: NKonrad Rzeszutek Wilk <konrad.wilk@oracle.com> Tested-by: NIan Campbell <ian.campbell@citrix.com>
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- 17 2月, 2011 6 次提交
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由 Ben Skeggs 提交于
This has been broken since 2.6.37, and fixes resume on a couple of fermi boards I have access to. Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
We free the temporary binding before leaving this function, so we also have to wait for the move to actually complete. Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
Due to the default case handling the older chipsets, a bunch of the newer ones ended up having the wrong tiling regs used. This commit switches the default case to handle the newest chipsets. This also makes nv4e touch the "extra" tiling regs. "nv" doesn't touch them for C51 but traces of the NVIDIA binary driver show it being done there. I couldn't find NV41/NV45 traces to confirm the behaviour there, but an educated guess was taken at each of them. Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
The DRM core fills this value, but at too late a stage for this to work, possibly resulting in an undesirable mode being selected. Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Francisco Jerez 提交于
Signed-off-by: NFrancisco Jerez <currojerez@riseup.net> Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Francisco Jerez 提交于
Reported-by: NAlex Buell <alex.buell@munted.org.uk> Signed-off-by: NFrancisco Jerez <currojerez@riseup.net> Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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