Don't leave runtime PM enabled in case devm_spi_register_controller()
returns with an error. Otherwise runtime PM will complain when driver is
reloaded:

[  693.855811] pxa2xx-spi pxa2xx-spi.13: Unbalanced pm_runtime_enable!
Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

gpiod_free() is an internal function for gpiolib, gpiod_put() is the
correct external function.
Reported-by: NStephen Rothwell <sfr@canb.auug.org.au>
Suggested-by: NRasmus Villemoes <linux@rasmusvillemoes.dk>
Signed-off-by: NMark Brown <broonie@kernel.org>

gpio_free(gpio) simply does gpiod_free(gpio_to_desc(gpio)), so it's
simpler and cleaner to use gpiod_free directly.
Signed-off-by: NRasmus Villemoes <linux@rasmusvillemoes.dk>
Signed-off-by: NMark Brown <broonie@kernel.org>

We still need to request/free GPIOs passed via the legacy path of
pxa2xx_spi_chip::gpio_cs, but we can use the gpiod API otherwise.

Consistently use the descriptor API instead of the legacy one.
Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com>
Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

GPIO descriptors, when being requested, may configure pin at the same
time. In case of SPI chip select we shouldn't do any assumptions of the
state of pin since we don't know yet what chip is connected there and if
it uses high or low active state. So, leave the state of pin as is until
transfer will start.

Fixes: 99f499cd ("spi: pxa2xx: Add support for GPIO descriptor chip selects")
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: NMika Westeberg <mika.westerberg@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

There is a valid case to call setup() following by setup_cs() several
times for the same chip.

With the commit

  676a4e3b ("spi: pxa2xx: Only claim CS GPIOs when the slave device is created")

it is not possible anymore due to GPIO line being requested already
during the first call to setup_cs().

For now, revert the commit to make things work again.
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Avoid hogging chip select GPIOs just because they are listed for the
master. They might be mulitplexed and, if no slave device is attached,
used for different purposes. Moreover, this strategy avoids having to
allocate a cs_gpiods structure.

Tested on the IOT2000 where the second SPI bus is connected to an
Arduino-compatible connector and multiplexed between SPI, GPIO and PWM
usage.
Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Intel Cannonlake LPSS SPI has up to four chip selects per port like in
Broxton and is clocked like Sunrisepoint and Kaby Lake. Add a new type
LPSS_CNL_SSP and configuration that enable runtime chip select detection
and use the same FIFO thresholds than in Sunrisepoint.

Patch adds support for both Cannonlake SoC and PCH.
Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

When using the a device with edge-triggered interrupts, such as MSIs,
the interrupt handler has to ensure that there is a point in time during
its execution where all interrupts sources are silent so that a new
event can trigger a new interrupt again.

This is achieved here by disabling all interrupt sources for a moment
before processing them according to the status register. If a new
interrupt should have arrived after we read the status, it will now
re-trigger the interrupt, even in edge mode.
Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com>
Acked-by: NRobert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: NMark Brown <broonie@kernel.org>

Gemini Lake reuses the same LPSS SPI configuration as Broxton
Signed-off-by: NDavid E. Box <david.e.box@linux.intel.com>
Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

As suggested by Andy Shevchenko: Decouple this corner cause from the
general handling logic in ssp_int.
Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

The commit 7c7289a4 ("spi: pxa2xx: Default thresholds to PXA
configuration") while splitting up CE4100 code obviously missed a break
condition in one chunk. Add it here.

Looks like we have no active user of CE4100, though better to fix this later
than never.

Fixes: commit 7c7289a4 ("spi: pxa2xx: Default thresholds to PXA configuration")
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Kbuild test robot reports:

  drivers/spi/spi-pxa2xx.c: In function ‘setup_cs’:
  drivers/spi/spi-pxa2xx.c:1190:20: error: implicit declaration of function ‘desc_to_gpio’
  ...

Reason for this is the fact that those functions are declared in
linux/gpio/consumer.h which is not included in the driver. Fix this by
including it.
Reported-by: Nkbuild test robot <fengguang.wu@intel.com>
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

The driver uses custom chip_info coming from platform data for chip selects
implemented as GPIOs. If the system lacks board files setting up the
platform data, it is not possible to use GPIOs as chip selects.

This adds support for GPIO descriptors so that regardless of the underlying
firmware interface (DT, ACPI or platform data) the driver can request GPIOs
used as chip selects and configure them accordingly.

The custom chip_info GPIO support is still left there to make sure the
existing systems keep working as expected.
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Most of the devices in the supported list have PXA configuration of FIFO. In
particularly Intel Medfield and Merrifield have bigger FIFO, than it's defined
for CE4100.

Split CE4100 in the similar way how it was done for Intel Quark, i.e. prefix
definitions by CE4100 and append necessary pieces of code to switch case
conditions.

We are on safe side since those bits are ignored on all LPSS IPs.
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Transfer state machine in this driver does not need to set/unset pointer
to chip data between queueing and finalizing message as it is not
actually used as a state info itself but just pointer passing.

Since this per SPI device specific chip data is already carried in
ctldata use that and remove pointer to chip data from driver data.

While at it, group initialized variables before uninitialized variables
in pump_transfers().
Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

There is no need to carry pointer to current SPI message in driver data
because cur_msg in struct spi_master holds it already when driver is using
the message queueing infrastructure from the SPI core.
Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

All of these variables are unconditionally set before their use.
Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

It seems the commit e5262d05 ("spi: spi-pxa2xx: SPI support for Intel Quark
X1000") misses one place to be adapted for Intel Quark, i.e. in reset_sccr1().

Clear all RFT bits when call reset_sccr1() on Intel Quark.

Fixes: e5262d05 ("spi: spi-pxa2xx: SPI support for Intel Quark X1000")
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>
Cc: stable@vger.kernel.org

Kaby Lake PCH-H has the same SPI host controller as Skylake. Add these new
PCI IDs to the list of supported devices.
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

SPI core provides DMA mapping with scatterlists. Start using it instead
of own implementation in spi-pxa2xx. Major difference in addition to
bunch of removed boilerplate code is that SPI core does
mapping/unmapping for all transfers in a message before and after the
message sending where spi-pxa2xx did mapping/unmapping for each
transfers separately.
Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

We will find more use for struct spi_master pointer in pump_transfers()
and code will be more readable if we access it using local pointer than
through the drv_data->master.
Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Currently, even if the PXA2xx SPI master supports DMA, it won't be
enabled unless (i) the slave device is enumerated through ACPI, or
(ii) the slave device is registered with board-specific
controller_data specified.  Even then, there isn't a field in the
controller_data that explicitly enables dma - it just gets enabled
if the master supports it and controller_data is non-NULL.

This means that drivers which register SPI devices on a bus without
awareness of this controller cannot avail of DMA performance gains.

This patch allows DMA transfers to be used if supported.
Signed-off-by: NDan O'Donovan <dan@emutex.com>
Reviewed-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

It's done by spi_alloc_master().
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Certain Intel Sunrisepoint PCH variants report zero chip selects in SPI
capabilities register even they have one per port. Detection in
pxa2xx_spi_probe() sets master->num_chipselect to 0 leading to -EINVAL
from spi_register_master() where chip select count is validated.

Fix this by not using SPI capabilities register on Sunrisepoint. They don't
have more than one chip select so use the default value 1 instead of
detection.

Fixes: 8b136baa ("spi: pxa2xx: Detect number of enabled Intel LPSS SPI chip select signals")
Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>
Cc: stable@vger.kernel.org

Fix cs_change management so that it is in line with other spi drivers.

In the spi core api helpers such as spi_bus_lock/unlock and spi_sync_locked
or cs_change field in spi_transfer help to manage chip select from the
device driver.

The driver was setting the chip select to idle if the message queue was
empty despite cs_change or other status field set by spi_bus_lock/unlock
or spi_sync_locked.
Signed-off-by: NChristophe Ricard <christophe-h.ricard@st.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Dummy buffer is used for half duplex transfers that don't have TX or RX
buffer set. Instead of own dummy buffer management here let the SPI core to
handle it by setting the SPI_MASTER_MUST_RX and SPI_MASTER_MUST_TX flags.
Then core makes sure both transfer buffers are set.
Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

If by some reason pxa2xx_spi_dma_prepare() fails we have not to ignore its
error. In such case we abort the transfer and return the error to upper
level.
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
[Jarkko: Avoid leaking TX descriptors in case RX descriptor allocation
fails. Noted by Robert Jarzmik <robert.jarzmik@free.fr>.
Unmap also buffers in case of failure.]
Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Acked-by: NRobert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: NMark Brown <broonie@kernel.org>

Add support for third Intel Broxton variant and update comment for
A-Step variant.
Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Tested-by: NSteve Sakoman <steve.sakoman@intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Only legacy PXA DMA implementation was using these rx_dma and tx_dma DMA
addresses so they are not needed after commit 6356437e
("spi: spi-pxa2xx: remove legacy PXA DMA bits").
Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Intel Braswell LPSS SPI controller actually has two chip selects and there
is no capabilities register where this could be found out. These two chip
selects are controlled by bits which are in slightly differrent location
than Broxton has.

Braswell Windows driver also starts chip select (ACPI DeviceSelection)
numbering from 1 so translate it to be suitable for Linux as well.
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Reviewed-by: NAndy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Some Intel LPSS SPI controllers, like the one in Braswell has these bits in
a different location so move these bits to be part of the LPSS
configuration.

Since not all LPSS SPI controllers support multiple native chip selects we
refactor selecting chip select to its own function and check
control->cs_sel_mask before switching to another chip select.
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Reviewed-by: NAndy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

The Windows Baytrail SPI host controller driver uses 1 as the first (and
only) value for ACPI DeviceSelection like can be seen in DSDT taken from
Lenovo Thinkpad 10:

    Device (FPNT)
    {
        ...
        Method (_CRS, 0, NotSerialized)  // _CRS: Current Resource Settings
        {
            Name (UBUF, ResourceTemplate ()
            {
                SpiSerialBus (0x0001, // DeviceSelection
                    PolarityLow, FourWireMode, 0x08,
                    ControllerInitiated, 0x007A1200, ClockPolarityLow,
                    ClockPhaseFirst, "\\_SB.SPI1",
                    0x00, ResourceConsumer,,)

This will fail to enumerate in Linux with following error:

[    0.241296] pxa2xx-spi 80860F0E:00: cs1 >= max 1
[    0.241312] spi_master spi32766: failed to add SPI device VFSI6101:00 from ACPI

To make the Linux SPI core successfully enumerate the device we provide a
custom version of ->fw_translate_cs() that translates DeviceSelection
correctly.
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Reviewed-by: NAndy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

There is a chance that chipselect is deasserted too early while the last
clock cycle is still running. Protocol analyzers will see this as a failed
last byte. This is more likely to occur with slow bitrates, for instance
at 25 kbps.

Reason for this is when using SPI mode 0 that both SPI host controller and
SPI slave will drive the data lines at the falling edge of clock signal
and sample at the rising edge. Receive FIFO gets the last bit now at the
rising edge and code sees transfer to be finished either by the interrupt
in PIO mode or by the DMA completion in DMA mode.

The SSP Time Out register SSTO should take care of delaying the
completion but it does not seems to have effect at least on Intel
Skylake and Broxton even when using long enough values. Depending on
timing code may get into point where chipselect is deasserted while the
last clock cycle is still running at its second half cycle.

Fix this by adding a wait loop in giveback() that waits until SSP becomes
idle before deasserting the chipselect.
Reported-by: NWeifeng Voon <weifeng.voon@intel.com>
Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

The register writes here actually don't stop the SSP but clean and
disable interrupts and set the receive FIFO inactivity timeout to zero.
Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Transfer debug messages don't actually show is the transfer really using
DMA. Driver may fall back to PIO in case transfer size is not within the
certain limits or fails to map DMA buffers but debug messages don't reveal
that.

Move these debug messages further in pump_transfers() where the actual
transfer mode is known and use drv_data->dma_mapped flag instead of
chip->enable_dma for printing the mode.
Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Commit 8b136baa ("spi: pxa2xx: Detect number of enabled Intel LPSS SPI
chip select signals") added a block where lpss_ssp_setup() gets called
again for Intel LPSS SPI host controllers before checking number of chip
selects from the capabilities register.

There is no point in calling the function twice in probe so remove the
first call.
Reported-by: NAaron Lu <aaron.lu@intel.com>
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Extend the pxa2xx_spi_acpi_get_pdata() so that it can create platform data
also on platforms that do not support ACPI or if CONFIG_ACPI is not set.
Now it is expected that "pxa2xx-spi" platform device is either created with
explicit platform data or has an ACPI companion device.

However there is only little in pxa2xx_spi_acpi_get_pdata() that is really
dependent on ACPI companion and it can be reworked to cover also cases
where "pxa2xx-spi" device doesn't have ACPI companion and is created
without platform data.

Do this by renaming the pxa2xx_spi_acpi_get_pdata(), moving it outside of
CONFIG_ACPI test and changing a few runtime tests there to support non-ACPI
case. Only port/bus ID setting based on ACPI _UID is dependent on ACPI and
is moved to own function inside CONFIG_ACPI.

Purpose of this to support non-ACPI case for those PCI enumerated compound
devices that integrate both LPSS SPI host controller and integrated DMA
engine under the same PCI ID and which are registered in MFD layer instead
of in spi-pxa2xx-pci.c.
Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

LPSS SPI in Intel Broxton is otherwise the same than in Intel Sunrisepoint
but it supports up to four chip selects per port and has different FIFO
thresholds. Patch adds support for two Broxton SoC variants.
Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

SPI capabilities register located in private registers space of newer
Intel LPSS SPI host controllers tell in register bits 12:9 which chip
select signals are enabled.

Use that information for detecting the number of chip selects. For
simplicity we assume chip selects are enabled one after another without
disabled chip selects between. For instance CS0 | CS1 | CS2 but not
CS0 | CS1 | CS3.
Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>