1. 22 6月, 2017 1 次提交
  2. 20 6月, 2017 21 次提交
  3. 19 6月, 2017 3 次提交
    • K
      clk: mvebu: cp110: add sdio clock to cp-110 system controller · a45af6d3
      Konstantin Porotchkin 提交于
      This commit updates the CP110 system controller driver to add the
      definition for a missing clock.
      
      The SDIO clock is dedicated driving the SDHCI interface and its frequency
      is 400MHz (2/5 of PLL source clock).
      
      The SDIO interface should be bound to this clock and not the core clock
      as in the older code.
      Using the wrong clock lead to a maximum SDHCI frequency of 250 Mhz, while
      the HW really supports up to 400 Mhz.
      
      This patch also fixes the NAND clock relationship documentation.
      Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com>
      [gregory.clement@free-electrons.com:
      - use sdio instead of emmc to name the clock]
      Reviewed-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
      Acked-by: NRob Herring <robh@kernel.org>
      Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
      a45af6d3
    • G
      clk: mvebu: cp110: introduce a new binding · 5ffeb5f5
      Gregory CLEMENT 提交于
      The initial intent when the binding of the cp110 system controller was to
      have one flat node. The idea being that what is currently a clock-only
      driver in drivers would become a MFD driver, exposing the clock, GPIO and
      pinctrl functionality. However, after taking a step back, this would lead
      to a messy binding. Indeed, a single node would be a GPIO controller,
      clock controller, pinmux controller, and more.
      
      This patch adopts a more classical solution of a top-level syscon node
      with sub-nodes for the individual devices. The main benefit will be to
      have each functional block associated to its own sub-node where we can
      put its own properties.
      
      The introduction of the Armada 7K/8K is still in the early stage so the
      plan is to remove the old binding. However, we don't want to break the
      device tree compatibility for the few devices already in the field. For
      this we still keep the support of the legacy compatible string with a big
      warning in the kernel about updating the device tree.
      Reviewed-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
      Acked-by: NRob Herring <robh@kernel.org>
      Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
      5ffeb5f5
    • G
      clk: mvebu: cp110: do not depend anymore of the *-clock-output-names · f5667274
      Gregory CLEMENT 提交于
      Using the *-clock-output-names property was a convenient way to have a
      unique name for each clock even when there are multiple cp110 blocks
      as we can find on Armada 8K.
      
      However it has some drawbacks: the main one being a stronger link than
      necessary between the driver and the device tree. For example the clock
      name can't be changed, removed or moved. It is still the early stage of
      introduction of the Armada 7K/8K and the hardware is still not totally
      documented, especially for the clock part. By removing the use of
      *-clock-output-names it will be easier to add new clocks without breaking
      the compatibility.
      
      The name of each clock is now created by using its physical address as a
      prefix (as it was done for the platform device names). Thanks to this we
      have an automatic way to compute a unique name.
      Acked-by: NRob Herring <robh@kernel.org>
      Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
      f5667274
  4. 17 6月, 2017 6 次提交
  5. 15 6月, 2017 9 次提交
    • T
      clk: ti: omap4: add clkctrl clock data · 1c881b5a
      Tero Kristo 提交于
      Add data for omap4 clkctrl clocks, and register it within the clkctrl
      driver.
      Signed-off-by: NTero Kristo <t-kristo@ti.com>
      Acked-by: NTony Lindgren <tony@atomide.com>
      1c881b5a
    • T
      dt-bindings: clk: add omap4 clkctrl definitions · 70ab980f
      Tero Kristo 提交于
      Contains offsets for all omap4 clkctrl main and optional clocks.
      Signed-off-by: NTero Kristo <t-kristo@ti.com>
      Acked-by: NTony Lindgren <tony@atomide.com>
      70ab980f
    • T
      clk: ti: add support for clkctrl clocks · 88a17252
      Tero Kristo 提交于
      Previously, hwmod core has been used for controlling the hwmod level
      clocks directly. This has certain drawbacks, like being unable to share
      the clocks for multiple users, missing usecounting and generally being
      totally incompatible with the common clock framework.
      
      This patch adds support for clkctrl clocks for addressing the above
      issues. These support the modulemode handling, which will replace the
      direct hwmod clkctrl linkage. Any optional clocks are also supported,
      gate, mux and divider.
      Signed-off-by: NTero Kristo <t-kristo@ti.com>
      Acked-by: NTony Lindgren <tony@atomide.com>
      88a17252
    • T
      Documentation: dt-bindings: Add binding documentation for TI clkctrl clocks · 35395a9c
      Tony Lindgren 提交于
      Texas Instruments omap variant SoCs starting with omap4 have a clkctrl
      clock controller instance for each interconnect target module. The clkctrl
      controls functional and interface clocks for the module.
      
      The clkctrl clocks are currently handled by arch/arm/mach-omap2 hwmod code.
      With this binding and a related clock device driver we can start moving the
      clkctrl clock handling to live in drivers/clk/ti.
      
      Note that this binding allows keeping the clockdomain related parts out of
      drivers/clock. The CLKCTCTRL and DYNAMICDEP registers can be handled by
      a separate driver in drivers/soc/ti and genpd. If the clockdomain driver
      needs to know it's clocks, we can just set the the clkctrl device
      instances to be children of the related clockdomain device.
      
      Each clkctrl clock can have multiple optional gate clocks, and multiple
      optional mux clocks. To represent this in device tree, it seems that
      it is best done using four clock cells #clock-cells = <2> property.
      
      The reasons for using #clock-cells = <2> are:
      
      1. We need to specify the clkctrl offset from the instance base. Otherwise
         we end up with a large number of device tree nodes that need to be
         patched when new clocks are discovered in a clkctrl clock with minor
         hardware revision changes for example
      
      2. On omap5 CM_L3INIT_USB_HOST_HS_CLKCTRL has ten OPTFCLKEN bits. So we
         need to use a separate cell for optional gate clocks to avoid address
         space conflicts
      
      There is probably no need to list input clocks for each clkctrl clock
      instance in the binding. If we want to add them, the standard clocks
      binding can be used for that.
      
      For hardware reference, see omap4430 TRM "Table 3-1312. L4PER_CM2 Registers
      Mapping Summary" for example. It shows one instance of a clkctrl clock
      controller with multiple clkctrl registers.
      
      Cc: Paul Walmsley <paul@pwsan.com>
      Acked-by: NRob Herring <robh@kernel.org>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      Signed-off-by: NTero Kristo <t-kristo@ti.com>
      35395a9c
    • S
      Merge branch 'clk-fixes' into clk-next · 9c861f33
      Stephen Boyd 提交于
      * clk-fixes:
        clk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCM
        clk: sunxi-ng: h3: Export PLL_PERIPH0 clock for the PRCM
        dt-bindings: clock: sunxi-ccu: Add pll-periph to PRCM's needed clocks
        clk: sunxi-ng: enable SUNXI_CCU_MP for PRCM
        clk: sunxi-ng: v3s: Fix usb otg device reset bit
        clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset
      9c861f33
    • S
      Merge tag 'sunxi-clk-fixes-for-4.12' of... · 949bdfed
      Stephen Boyd 提交于
      Merge tag 'sunxi-clk-fixes-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes
      
      Allwinner clock fixes for 4.12
      
      Some fixes that fix some bindings that went in 4.12, fix a few reset and
      clock offsets and a build error fix
      
      * tag 'sunxi-clk-fixes-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
        clk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCM
        clk: sunxi-ng: h3: Export PLL_PERIPH0 clock for the PRCM
        dt-bindings: clock: sunxi-ccu: Add pll-periph to PRCM's needed clocks
        clk: sunxi-ng: enable SUNXI_CCU_MP for PRCM
        clk: sunxi-ng: v3s: Fix usb otg device reset bit
        clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset
      949bdfed
    • S
      Merge tag 'clk-v4.13-samsung' of... · 7f274d54
      Stephen Boyd 提交于
      Merge tag 'clk-v4.13-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-next
      
      Pull samsung clk driver updates from Sylwester Nawrocki
      
       - conversion to the clk_hw API
       - definitions and fixes of exynos5420 SoC audio subsystem
         related clocks
      
      * tag 'clk-v4.13-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
        clk: samsung: exynos542x: Add EPLL rate table
        clk: samsung: Add missing exynos5420 audio related clocks
        clk: samsung: Add enable/disable operation for PLL36XX clocks
        clk: samsung: s5pv210-audss: Convert to the new clk_hw API
        clk: samsung: exynos-clkout: Convert to the new clk_hw API
        clk: samsung: exynos-audss: Convert to the new clk_hw API
        clk: samsung: Convert common drivers to the new clk_hw API
        clk: samsung: Add local variable to match its purpose
        clk: samsung: Remove dead code
      7f274d54
    • S
      Merge tag 'v4.13-rockchip-clk1' of... · c96da4dd
      Stephen Boyd 提交于
      Merge tag 'v4.13-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
      
      Pull rockchip clk driver updates from Heiko Stuebner:
      
      One new clock controller for the rk3128 soc, a fixup for the rk3228 cpuclk
      table and the usual bunch of some new clock-ids and some clocks marked as
      critical.
      
      * tag 'v4.13-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
        clk: rockchip: mark some special clk as critical on rk3368
        clk: rockchip: mark noc and some special clk as critical on rk3288
        clk: rockchip: mark noc and some special clk as critical on rk3228
        clk: rockchip: mark pclk_ddrupctl as critical_clock on rk3036
        clk: rockchip: add clock controller for rk3128
        dt-bindings: add bindings for rk3128 clock controller
        clk: rockchip: export more rk3228 clocks ids
        clk: rockchip: add ids for rk3399 testclks used for camera handling
        clk: rockchip: add dt-binding header for rk3128
        clk: rockchip: fix up the RK3228 clk cpu setting table
        clk: rockchip: add clock-ids for more rk3228 clocks
        clk: rockchip: add ids for camera on rk3399
      c96da4dd
    • T
      clk: keystone: Add sci-clk driver support · b745c079
      Tero Kristo 提交于
      In K2G, the clock handling is done through firmware executing on a
      separate core. Linux kernel needs to communicate to the firmware
      through TI system control interface to access any power management
      related resources, including clocks.
      
      The keystone sci-clk driver does this, by communicating to the
      firmware through the TI SCI driver. The driver adds support for
      registering clocks through DT, and basic required clock operations
      like prepare/get_rate, etc.
      Signed-off-by: NTero Kristo <t-kristo@ti.com>
      [sboyd@codeaurora.org: Make ti_sci_init_clocks() static]
      Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
      b745c079
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