- 22 6月, 2017 1 次提交
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由 Stephen Boyd 提交于
Now that this function is called from driver probe routines, it needs to drop the __init marking because it isn't just called from init code. Reported-by: NStephen Rothwell <sfr@canb.auug.org.au> Cc: Sandeep Tripathy <sandeep.tripathy@broadcom.com> Cc: Anup Patel <anup.patel@broadcom.com> Cc: Ray Jui <ray.jui@broadcom.com> Cc: Scott Branden <scott.branden@broadcom.com> Fixes: 654cdd32 ("clk: bcm: Add clocks for Stingray SOC") Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 20 6月, 2017 21 次提交
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由 Sandeep Tripathy 提交于
This patch adds support for Stingray clocks in iproc ccf. The Stingray SOC has various plls based on iproc pll architecture. Signed-off-by: NSandeep Tripathy <sandeep.tripathy@broadcom.com> Signed-off-by: NAnup Patel <anup.patel@broadcom.com> Reviewed-by: NRay Jui <ray.jui@broadcom.com> Reviewed-by: NScott Branden <scott.branden@broadcom.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Sandeep Tripathy 提交于
Update iproc clock dt-binding documentation with Stingray pll and clock details. Signed-off-by: NSandeep Tripathy <sandeep.tripathy@broadcom.com> Reviewed-by: NRay Jui <ray.jui@broadcom.com> Reviewed-by: NScott Branden <scott.branden@broadcom.com> Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Sean Wang 提交于
The patch enables CPU multiplexer clock on MT8173 SoC which fixes up cpufreq driver fails at acquiring intermediate clock source when driver probe is called. Signed-off-by: NPi-Cheng Chen <pi-cheng.chen@linaro.org> Signed-off-by: NSean Wang <sean.wang@mediatek.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Sean Wang 提交于
The patch enables CPU multiplexer clock on MT2701/MT7623 SoC which fixes up cpufreq driver fails at acquiring intermediate clock source when driver probe is called. Signed-off-by: NPi-Cheng Chen <pi-cheng.chen@linaro.org> Signed-off-by: NSean Wang <sean.wang@mediatek.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Sean Wang 提交于
This patch adds CPU multiplexer clocks which are essential for Mediatek cpufreq driver. It would use the CPU clock multiplexer to switch to the intermediate clock source temporarily and then wait for the primary clock changing getting stable. Signed-off-by: NPi-Cheng Chen <pi-cheng.chen@linaro.org> Signed-off-by: NSean Wang <sean.wang@mediatek.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Geert Uytterhoeven 提交于
If CONFIG_OF=n: drivers/clk/renesas/renesas-cpg-mssr.c: In function ‘cpg_mssr_probe’: drivers/clk/renesas/renesas-cpg-mssr.c:702: warning: dereferencing ‘void *’ pointer drivers/clk/renesas/renesas-cpg-mssr.c:702: error: request for member ‘data’ in something not a structure or union To fix this, use the of_device_get_match_data() helper, for which a dummy version is provided if CONFIG_OF=n. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Zhangfei Gao 提交于
Add acpu clock, including sft clock controlling hi6220 coresight module Signed-off-by: NZhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: NLi Pengcheng <lipengcheng8@huawei.com> Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Shawn Guo 提交于
Export I2S mux clocks, so that device tree can refer to them for setting a better parent clock for I2S work clock. Signed-off-by: NShawn Guo <shawn.guo@linaro.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Stefan Agner 提交于
The rawnand clock gate gates two clocks, NAND_USDHC_BUS_CLK_ROOT and NAND_CLK_ROOT. However, the gate has been in the chain of the latter only. This does not allow to use the NAND_USDHC_BUS_CLK_ROOT only, e.g. as required by APBH-Bridge-DMA. Add new clocks which represent the clock after the gate, and use a shared clock gate to correctly model the hardware. Signed-off-by: NStefan Agner <stefan@agner.ch> Tested-by: NFabio Estevam <fabio.estevam@nxp.com> Acked-by: NHan Xu <han.xu@nxp.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Zhong Kaihua 提交于
Set PPLL2 to 2880M. With this patch, we saw better compatibility on various 1080p HDMI monitors. Signed-off-by: NZhong Kaihua <zhongkaihua@huawei.com> Signed-off-by: NZheng Shaobo <zhengshaobo1@huawei.com> Acked-by: NZhangfei Gao <zhangfei.gao@linaro.org> [sboyd@codeaurora.org: Add UL to long number to silence C90 warning] Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Chen Jun 提交于
This patch adds more clocks for hi3660, including: - video encoder and decoder - ISP (Image Signal Processing) Signed-off-by: NChen Jun <chenjun14@huawei.com> Signed-off-by: NZhong Kaihua <zhongkaihua@huawei.com> Signed-off-by: NGuodong Xu <guodong.xu@linaro.org> Reviewed-by: NZhangfei Gao <zhangfei.gao@linaro.org> Acked-by: NZhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Chen Jun 提交于
Parent name of clk_mux_sysbus is not correct. This patch fixes it. Signed-off-by: NChen Jun <chenjun14@huawei.com> Signed-off-by: NJohn Stultz <john.stultz@linaro.org> Signed-off-by: NGuodong Xu <guodong.xu@linaro.org> Acked-by: NZhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Srinivas Kandagatla 提交于
MCLK for internal audio codec is expected to be at 9.6MHz by default. This patch adds support to 9.6MHz to make the default case possible. Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Abhishek Sahu 提交于
This patch adds support for the global clock controller found on the ipq8074 based devices. This includes UART, I2C, SPI etc. Signed-off-by: NAbhishek Sahu <absahu@codeaurora.org> Signed-off-by: NVaradarajan Narayanan <varada@codeaurora.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Abhishek Sahu 提交于
Add the compatible strings and the include file for ipq8074 gcc clock controller. Acked-by: Rob Herring <robh@kernel.org> (bindings) Signed-off-by: NVaradarajan Narayanan <varada@codeaurora.org> Signed-off-by: NAbhishek Sahu <absahu@codeaurora.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Linus Walleij 提交于
This adds the DT binding macros used by the clock controller. Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Linus Walleij 提交于
This adds the DT binding macros used by the reset controller. Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Stephen Boyd 提交于
Mark an array of strings static const and remove the dereference of a function pointer when assigning to the platform driver probe struct member. drivers/clk/mvebu/cp110-system-controller.c:89:12: warning: symbol 'gate_base_names' was not declared. Should it be static? drivers/clk/mvebu/cp110-system-controller.c:447:18: error: cannot dereference this type Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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git://git.infradead.org/linux-mvebu由 Stephen Boyd 提交于
Pull improved Marvel Armada 7K/8K cp110 clk support from Gregory CLEMENT: We got more information about the clock controllers and the clock tree of the CP110 part that we find in the Marvell Armada 7K/8K SoCs. The clk driver is modified accordingly from this new information. * 'clk-cp110' of git://git.infradead.org/linux-mvebu: clk: mvebu: cp110: add sdio clock to cp-110 system controller clk: mvebu: cp110: introduce a new binding clk: mvebu: cp110: do not depend anymore of the *-clock-output-names clk: mvebu: cp110: make failure labels more meaningful
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由 Dinh Nguyen 提交于
The smplsel bits for the SDMMC clock on Arria10 and Stratix10 platforms are offset by 1 additional bit. Add a new macro SYSMGR_SDMMC_CTRL_SET_AS10 for usage on the Arria10 and Stratix10 platforms. Fixes: 5611a5ba ("clk: socfpga: update clk.h so for Arria10 platform to use") Signed-off-by: NDinh Nguyen <dinguyen@kernel.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Leo Yan 提交于
The timer will register into system at very early phase at kernel boot; if timer needs to use clock, the clock should be get ready in function of_clk_init() so later the timer driver probe can retrieve clock successfully. This is finished in below flow on arm64: start_kernel() `-> time_init() `-> of_clk_init(NULL) => register timer's clock `-> clocksource_probe() => register timer On Hi3660 the sp804 timer uses clock "osc32k", this clock is registered as platform driver rather than CLK_OF_DECLARE_DRIVER method. As result, sp804 timer probe returns failure due if cannot bind clock properly. To fix the failure, this patch is to split crgctrl clocks into two subsets. One part is for fixed_rate_clks which includes pre-defined fixed rate clocks, and "osc32k" clock is in this category; So we change their registration to CLK_OF_DECLARE_DRIVER method, as result the clocks can be registered ahead with function of_clk_init() and timer driver can bind timer clock successfully; the rest of the crgctrl clocks are still registered by the probe of the platform driver. This patch also adds checking for all crgctrl clocks registration and print out log if any clock has failure. Signed-off-by: NLeo Yan <leo.yan@linaro.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 19 6月, 2017 3 次提交
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由 Konstantin Porotchkin 提交于
This commit updates the CP110 system controller driver to add the definition for a missing clock. The SDIO clock is dedicated driving the SDHCI interface and its frequency is 400MHz (2/5 of PLL source clock). The SDIO interface should be bound to this clock and not the core clock as in the older code. Using the wrong clock lead to a maximum SDHCI frequency of 250 Mhz, while the HW really supports up to 400 Mhz. This patch also fixes the NAND clock relationship documentation. Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com> [gregory.clement@free-electrons.com: - use sdio instead of emmc to name the clock] Reviewed-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
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由 Gregory CLEMENT 提交于
The initial intent when the binding of the cp110 system controller was to have one flat node. The idea being that what is currently a clock-only driver in drivers would become a MFD driver, exposing the clock, GPIO and pinctrl functionality. However, after taking a step back, this would lead to a messy binding. Indeed, a single node would be a GPIO controller, clock controller, pinmux controller, and more. This patch adopts a more classical solution of a top-level syscon node with sub-nodes for the individual devices. The main benefit will be to have each functional block associated to its own sub-node where we can put its own properties. The introduction of the Armada 7K/8K is still in the early stage so the plan is to remove the old binding. However, we don't want to break the device tree compatibility for the few devices already in the field. For this we still keep the support of the legacy compatible string with a big warning in the kernel about updating the device tree. Reviewed-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
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由 Gregory CLEMENT 提交于
Using the *-clock-output-names property was a convenient way to have a unique name for each clock even when there are multiple cp110 blocks as we can find on Armada 8K. However it has some drawbacks: the main one being a stronger link than necessary between the driver and the device tree. For example the clock name can't be changed, removed or moved. It is still the early stage of introduction of the Armada 7K/8K and the hardware is still not totally documented, especially for the clock part. By removing the use of *-clock-output-names it will be easier to add new clocks without breaking the compatibility. The name of each clock is now created by using its physical address as a prefix (as it was done for the platform device names). Thanks to this we have an automatic way to compute a unique name. Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
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- 17 6月, 2017 6 次提交
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git://github.com/BayLibre/clk-meson由 Stephen Boyd 提交于
Pull Amlogic clk driver updates from Jerome Brunet: * Expose more clock gate on meson8 (SAR ADC, RNG, USB, SDIO, ETH) * Add new compatible to the meson8 clock controller for meson8b * Add missing parents to gxbb clk81 * tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson: clk: meson: gxbb: add all clk81 parents clk: meson: meson8b: add compatibles for Meson8 and Meson8m2 clk: meson8b: export the ethernet gate clock clk: meson8b: export the USB clocks clk: meson8b: export the gate clock for the HW random number generator clk: meson8b: export the SDIO clock clk: meson8b: export the SAR ADC clocks
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https://github.com/t-kristo/linux-pm由 Stephen Boyd 提交于
* 'for-4.13-ti-clkctrl' of https://github.com/t-kristo/linux-pm: clk: ti: omap4: add clkctrl clock data dt-bindings: clk: add omap4 clkctrl definitions clk: ti: add support for clkctrl clocks Documentation: dt-bindings: Add binding documentation for TI clkctrl clocks
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由 Stephen Boyd 提交于
It isn't used outside of this file right now. Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Stephen Boyd 提交于
Merge tag 'sunxi-clk-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next Pull Allwinner clock patches from Maxime Ripard: Some new clock units are supported, for the display clocks unsed in the newer SoCs, and the A83T PRCM. There is also a bunch of minor fixes for clocks that are not used by anyone, and reworks needed by drivers that will land in 4.13. * tag 'sunxi-clk-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (21 commits) clk: sunxi-ng: Move all clock types to a library clk: sunxi-ng: a83t: Add support for A83T's PRCM dt-bindings: clock: sunxi-ccu: Add compatible string for A83T PRCM clk: sunxi-ng: select SUNXI_CCU_MULT for sun8i-a83t clk: sunxi-ng: a83t: Fix audio PLL divider offset clk: sunxi-ng: a83t: Fix PLL lock status register offset clk: sunxi-ng: Add driver for A83T CCU clk: sunxi-ng: Support multiple variable pre-dividers dt-bindings: clock: sunxi-ccu: Add compatible string for A83T CCU clk: sunxi-ng: de2: fix wrong pointer passed to PTR_ERR() clk: sunxi-ng: sun5i: Export video PLLs clk: sunxi-ng: mux: Re-adjust parent rate clk: sunxi-ng: mux: Change pre-divider application function prototype clk: sunxi-ng: mux: split out the pre-divider computation code clk: sunxi-ng: mux: Don't just rely on the parent for CLK_SET_RATE_PARENT clk: sunxi-ng: div: Switch to divider_round_rate clk: sunxi-ng: Pass the parent and a pointer to the clocks round rate clk: divider: Make divider_round_rate take the parent clock clk: sunxi-ng: explicitly include linux/spinlock.h clk: sunxi-ng: add support for DE2 CCU ...
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由 Jerome Brunet 提交于
Remove the FIXME on clk81 mux and add all the documented parents Acked-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
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由 Jerome Brunet 提交于
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- 15 6月, 2017 9 次提交
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由 Tero Kristo 提交于
Add data for omap4 clkctrl clocks, and register it within the clkctrl driver. Signed-off-by: NTero Kristo <t-kristo@ti.com> Acked-by: NTony Lindgren <tony@atomide.com>
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由 Tero Kristo 提交于
Contains offsets for all omap4 clkctrl main and optional clocks. Signed-off-by: NTero Kristo <t-kristo@ti.com> Acked-by: NTony Lindgren <tony@atomide.com>
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由 Tero Kristo 提交于
Previously, hwmod core has been used for controlling the hwmod level clocks directly. This has certain drawbacks, like being unable to share the clocks for multiple users, missing usecounting and generally being totally incompatible with the common clock framework. This patch adds support for clkctrl clocks for addressing the above issues. These support the modulemode handling, which will replace the direct hwmod clkctrl linkage. Any optional clocks are also supported, gate, mux and divider. Signed-off-by: NTero Kristo <t-kristo@ti.com> Acked-by: NTony Lindgren <tony@atomide.com>
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由 Tony Lindgren 提交于
Texas Instruments omap variant SoCs starting with omap4 have a clkctrl clock controller instance for each interconnect target module. The clkctrl controls functional and interface clocks for the module. The clkctrl clocks are currently handled by arch/arm/mach-omap2 hwmod code. With this binding and a related clock device driver we can start moving the clkctrl clock handling to live in drivers/clk/ti. Note that this binding allows keeping the clockdomain related parts out of drivers/clock. The CLKCTCTRL and DYNAMICDEP registers can be handled by a separate driver in drivers/soc/ti and genpd. If the clockdomain driver needs to know it's clocks, we can just set the the clkctrl device instances to be children of the related clockdomain device. Each clkctrl clock can have multiple optional gate clocks, and multiple optional mux clocks. To represent this in device tree, it seems that it is best done using four clock cells #clock-cells = <2> property. The reasons for using #clock-cells = <2> are: 1. We need to specify the clkctrl offset from the instance base. Otherwise we end up with a large number of device tree nodes that need to be patched when new clocks are discovered in a clkctrl clock with minor hardware revision changes for example 2. On omap5 CM_L3INIT_USB_HOST_HS_CLKCTRL has ten OPTFCLKEN bits. So we need to use a separate cell for optional gate clocks to avoid address space conflicts There is probably no need to list input clocks for each clkctrl clock instance in the binding. If we want to add them, the standard clocks binding can be used for that. For hardware reference, see omap4430 TRM "Table 3-1312. L4PER_CM2 Registers Mapping Summary" for example. It shows one instance of a clkctrl clock controller with multiple clkctrl registers. Cc: Paul Walmsley <paul@pwsan.com> Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NTero Kristo <t-kristo@ti.com>
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由 Stephen Boyd 提交于
* clk-fixes: clk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCM clk: sunxi-ng: h3: Export PLL_PERIPH0 clock for the PRCM dt-bindings: clock: sunxi-ccu: Add pll-periph to PRCM's needed clocks clk: sunxi-ng: enable SUNXI_CCU_MP for PRCM clk: sunxi-ng: v3s: Fix usb otg device reset bit clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset
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由 Stephen Boyd 提交于
Merge tag 'sunxi-clk-fixes-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes Allwinner clock fixes for 4.12 Some fixes that fix some bindings that went in 4.12, fix a few reset and clock offsets and a build error fix * tag 'sunxi-clk-fixes-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCM clk: sunxi-ng: h3: Export PLL_PERIPH0 clock for the PRCM dt-bindings: clock: sunxi-ccu: Add pll-periph to PRCM's needed clocks clk: sunxi-ng: enable SUNXI_CCU_MP for PRCM clk: sunxi-ng: v3s: Fix usb otg device reset bit clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset
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由 Stephen Boyd 提交于
Merge tag 'clk-v4.13-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-next Pull samsung clk driver updates from Sylwester Nawrocki - conversion to the clk_hw API - definitions and fixes of exynos5420 SoC audio subsystem related clocks * tag 'clk-v4.13-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk: clk: samsung: exynos542x: Add EPLL rate table clk: samsung: Add missing exynos5420 audio related clocks clk: samsung: Add enable/disable operation for PLL36XX clocks clk: samsung: s5pv210-audss: Convert to the new clk_hw API clk: samsung: exynos-clkout: Convert to the new clk_hw API clk: samsung: exynos-audss: Convert to the new clk_hw API clk: samsung: Convert common drivers to the new clk_hw API clk: samsung: Add local variable to match its purpose clk: samsung: Remove dead code
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由 Stephen Boyd 提交于
Merge tag 'v4.13-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull rockchip clk driver updates from Heiko Stuebner: One new clock controller for the rk3128 soc, a fixup for the rk3228 cpuclk table and the usual bunch of some new clock-ids and some clocks marked as critical. * tag 'v4.13-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: mark some special clk as critical on rk3368 clk: rockchip: mark noc and some special clk as critical on rk3288 clk: rockchip: mark noc and some special clk as critical on rk3228 clk: rockchip: mark pclk_ddrupctl as critical_clock on rk3036 clk: rockchip: add clock controller for rk3128 dt-bindings: add bindings for rk3128 clock controller clk: rockchip: export more rk3228 clocks ids clk: rockchip: add ids for rk3399 testclks used for camera handling clk: rockchip: add dt-binding header for rk3128 clk: rockchip: fix up the RK3228 clk cpu setting table clk: rockchip: add clock-ids for more rk3228 clocks clk: rockchip: add ids for camera on rk3399
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由 Tero Kristo 提交于
In K2G, the clock handling is done through firmware executing on a separate core. Linux kernel needs to communicate to the firmware through TI system control interface to access any power management related resources, including clocks. The keystone sci-clk driver does this, by communicating to the firmware through the TI SCI driver. The driver adds support for registering clocks through DT, and basic required clock operations like prepare/get_rate, etc. Signed-off-by: NTero Kristo <t-kristo@ti.com> [sboyd@codeaurora.org: Make ti_sci_init_clocks() static] Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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