1. 12 9月, 2018 6 次提交
  2. 29 8月, 2018 1 次提交
  3. 23 8月, 2018 1 次提交
  4. 22 8月, 2018 1 次提交
  5. 18 7月, 2018 1 次提交
  6. 13 7月, 2018 1 次提交
  7. 03 7月, 2018 1 次提交
    • T
      drm/i915: Wait for PSR exit before checking for vblank evasion · a6089879
      Tarun Vyas 提交于
      The PIPEDSL freezes on PSR entry and if PSR hasn't fully exited, then
      the pipe_update_start call schedules itself out to check back later.
      
      On ChromeOS-4.4 kernel, which is fairly up-to-date w.r.t drm/i915 but
      lags w.r.t core kernel code, hot plugging an external display triggers
      tons of "potential atomic update errors" in the dmesg, on *pipe A*. A
      closer analysis reveals that we try to read the scanline 3 times and
      eventually timeout, b/c PSR hasn't exited fully leading to a PIPEDSL
      stuck @ 1599. This issue is not seen on upstream kernels, b/c for *some*
      reason we loop inside intel_pipe_update start for ~2+ msec which in this
      case is more than enough to exit PSR fully, hence an *unstuck* PIPEDSL
      counter, hence no error. On the other hand, the ChromeOS kernel spends
      ~1.1 msec looping inside intel_pipe_update_start and hence errors out
      b/c the source is still in PSR.
      
      Regardless, we should wait for PSR exit (if PSR is disabled, we incur
      a ~1-2 usec penalty) before reading the PIPEDSL, b/c if we haven't
      fully exited PSR, then checking for vblank evasion isn't actually
      applicable.
      
      v4: Comment explaining psr_wait after enabling VBL interrupts (DK)
      
      v5: CAN_PSR() to handle platforms that don't support PSR.
      
      v6: Handle local_irq_disable on early return (Chris)
      Acked-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      Reviewed-by: NDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
      Signed-off-by: NTarun Vyas <tarun.vyas@intel.com>
      Signed-off-by: NDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20180627200250.1515-2-tarun.vyas@intel.com
      a6089879
  8. 09 6月, 2018 1 次提交
    • V
      drm/i915: Fix sprite destination colorkeying on SKL+ · 672b3c4b
      Ville Syrjälä 提交于
      On SKL+ the dst colorkey must be configured on the lower
      plane that contains the colorkey. This is in contrast to
      most earlier platforms where the dst colorkey is configured
      on the plane above.
      
      The hardware will peform dst keying only between two immediately
      adjacent (in zorder) planes. Plane 2 will be keyed against plane 1,
      plane 3 againts plane 2, and so on. There is no way to key arbitrary
      planes against plane 1. Thus offering dst color keying on plane 3+
      is pointless. In fact it can be harmful since enabling dst keying on
      more than one plane on the same pipe leads to only the top-most of
      the planes performing the keying. For any plane lower in zorder the
      dst key enable is simply ignored.
      
      v2: s/plane 0/plane 1/ etc. since the hw plane names start from 1
          Don't break dst colorkey on pre-SKL sprites (hunk ended in the
          wrong patch)
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20180529182804.8571-1-ville.syrjala@linux.intel.com
      Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> #v1
      672b3c4b
  9. 01 6月, 2018 3 次提交
  10. 31 5月, 2018 1 次提交
  11. 11 5月, 2018 2 次提交
  12. 04 5月, 2018 2 次提交
  13. 03 5月, 2018 1 次提交
  14. 09 4月, 2018 2 次提交
  15. 02 3月, 2018 5 次提交
  16. 10 2月, 2018 2 次提交
  17. 06 2月, 2018 1 次提交
  18. 30 1月, 2018 1 次提交
  19. 25 1月, 2018 1 次提交
  20. 23 1月, 2018 1 次提交
  21. 19 1月, 2018 4 次提交
  22. 15 1月, 2018 1 次提交