1. 15 1月, 2011 1 次提交
  2. 03 1月, 2011 1 次提交
  3. 08 10月, 2010 3 次提交
    • D
      async_tx: make async_tx channel switching opt-in · 5fc6d897
      Dan Williams 提交于
      The majority of drivers in drivers/dma/ will never establish cross
      channel operation chains and do not need the extra overhead in struct
      dma_async_tx_descriptor.  Make channel switching opt-in by default.
      
      Cc: Anatolij Gustschin <agust@denx.de>
      Cc: Ira Snyder <iws@ovro.caltech.edu>
      Cc: Linus Walleij <linus.walleij@stericsson.com>
      Cc: Saeed Bishara <saeed@marvell.com>
      Signed-off-by: NDan Williams <dan.j.williams@intel.com>
      5fc6d897
    • I
      fsldma: improved DMA_SLAVE support · 968f19ae
      Ira Snyder 提交于
      Now that the generic DMAEngine API has support for scatterlist to
      scatterlist copying, the device_prep_slave_sg() portion of the
      DMA_SLAVE API is no longer necessary and has been removed.
      
      However, the device_control() portion of the DMA_SLAVE API is still
      useful to control device specific parameters, such as externally
      controlled DMA transfers and maximum burst length.
      
      A special dma_ctrl_cmd has been added to enable externally controlled
      DMA transfers. This is currently specific to the Freescale DMA
      controller, but can easily be made generic when another user is found.
      Signed-off-by: NIra W. Snyder <iws@ovro.caltech.edu>
      Signed-off-by: NDan Williams <dan.j.williams@intel.com>
      968f19ae
    • I
      dma: add support for scatterlist to scatterlist copy · a86ee03c
      Ira Snyder 提交于
      This adds support for scatterlist to scatterlist DMA transfers. A
      similar interface is exposed by the fsldma driver (through the DMA_SLAVE
      API) and by the ste_dma40 driver (through an exported function).
      
      This patch paves the way for making this type of copy operation a part
      of the generic DMAEngine API. Futher patches will add support in
      individual drivers.
      Signed-off-by: NIra W. Snyder <iws@ovro.caltech.edu>
      Signed-off-by: NDan Williams <dan.j.williams@intel.com>
      a86ee03c
  4. 06 10月, 2010 2 次提交
  5. 23 9月, 2010 1 次提交
  6. 05 8月, 2010 1 次提交
  7. 18 5月, 2010 2 次提交
  8. 27 3月, 2010 3 次提交
    • D
      dmaengine: provide helper for setting txstate · bca34692
      Dan Williams 提交于
      Simple conditional struct filler to cut out some duplicated code.
      Signed-off-by: NDan Williams <dan.j.williams@intel.com>
      bca34692
    • L
      DMAENGINE: generic channel status v2 · 07934481
      Linus Walleij 提交于
      Convert the device_is_tx_complete() operation on the
      DMA engine to a generic device_tx_status()operation which
      can return three states, DMA_TX_RUNNING, DMA_TX_COMPLETE,
      DMA_TX_PAUSED.
      
      [dan.j.williams@intel.com: update for timberdale]
      Signed-off-by: NLinus Walleij <linus.walleij@stericsson.com>
      Acked-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
      Cc: Maciej Sosnowski <maciej.sosnowski@intel.com>
      Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
      Cc: Pavel Machek <pavel@ucw.cz>
      Cc: Li Yang <leoli@freescale.com>
      Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
      Cc: Paul Mundt <lethal@linux-sh.org>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
      Cc: Magnus Damm <damm@opensource.se>
      Cc: Liam Girdwood <lrg@slimlogic.co.uk>
      Cc: Joe Perches <joe@perches.com>
      Cc: Roland Dreier <rdreier@cisco.com>
      Signed-off-by: NDan Williams <dan.j.williams@intel.com>
      07934481
    • L
      DMAENGINE: generic slave control v2 · c3635c78
      Linus Walleij 提交于
      Convert the device_terminate_all() operation on the
      DMA engine to a generic device_control() operation
      which can now optionally support also pausing and
      resuming DMA on a certain channel. Implemented for the
      COH 901 318 DMAC as an example.
      
      [dan.j.williams@intel.com: update for timberdale]
      Signed-off-by: NLinus Walleij <linus.walleij@stericsson.com>
      Acked-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
      Cc: Maciej Sosnowski <maciej.sosnowski@intel.com>
      Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
      Cc: Pavel Machek <pavel@ucw.cz>
      Cc: Li Yang <leoli@freescale.com>
      Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
      Cc: Paul Mundt <lethal@linux-sh.org>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
      Cc: Magnus Damm <damm@opensource.se>
      Cc: Liam Girdwood <lrg@slimlogic.co.uk>
      Cc: Joe Perches <joe@perches.com>
      Cc: Roland Dreier <rdreier@cisco.com>
      Signed-off-by: NDan Williams <dan.j.williams@intel.com>
      c3635c78
  9. 01 3月, 2010 1 次提交
  10. 17 2月, 2010 1 次提交
    • T
      percpu: add __percpu sparse annotations to what's left · a29d8b8e
      Tejun Heo 提交于
      Add __percpu sparse annotations to places which didn't make it in one
      of the previous patches.  All converions are trivial.
      
      These annotations are to make sparse consider percpu variables to be
      in a different address space and warn if accessed without going
      through percpu accessors.  This patch doesn't affect normal builds.
      Signed-off-by: NTejun Heo <tj@kernel.org>
      Acked-by: NBorislav Petkov <borislav.petkov@amd.com>
      Cc: Dan Williams <dan.j.williams@intel.com>
      Cc: Huang Ying <ying.huang@intel.com>
      Cc: Len Brown <lenb@kernel.org>
      Cc: Neil Brown <neilb@suse.de>
      a29d8b8e
  11. 11 12月, 2009 1 次提交
  12. 09 9月, 2009 5 次提交
    • D
      dmaengine: kill tx_list · 08031727
      Dan Williams 提交于
      The tx_list attribute of struct dma_async_tx_descriptor is common to
      most, but not all dma driver implementations.  None of the upper level
      code (dmaengine/async_tx) uses it, so allow drivers to implement it
      locally if they need it.  This saves sizeof(struct list_head) bytes for
      drivers that do not manage descriptors with a linked list (e.g.: ioatdma
      v2,3).
      Signed-off-by: NDan Williams <dan.j.williams@intel.com>
      
      08031727
    • D
      dmaengine, async_tx: support alignment checks · 83544ae9
      Dan Williams 提交于
      Some engines have transfer size and address alignment restrictions.  Add
      a per-operation alignment property to struct dma_device that the async
      routines and dmatest can use to check alignment capabilities.
      Signed-off-by: NDan Williams <dan.j.williams@intel.com>
      83544ae9
    • D
      dmaengine: cleanup unused transaction types · 9308add6
      Dan Williams 提交于
      No drivers currently implement these operation types, so they can be
      deleted.
      Signed-off-by: NDan Williams <dan.j.williams@intel.com>
      9308add6
    • D
      dmaengine, async_tx: add a "no channel switch" allocator · 138f4c35
      Dan Williams 提交于
      Channel switching is problematic for some dmaengine drivers as the
      architecture precludes separating the ->prep from ->submit.  In these
      cases the driver can select ASYNC_TX_DISABLE_CHANNEL_SWITCH to modify
      the async_tx allocator to only return channels that support all of the
      required asynchronous operations.
      
      For example MD_RAID456=y selects support for asynchronous xor, xor
      validate, pq, pq validate, and memcpy.  When
      ASYNC_TX_DISABLE_CHANNEL_SWITCH=y any channel with all these
      capabilities is marked DMA_ASYNC_TX allowing async_tx_find_channel() to
      quickly locate compatible channels with the guarantee that dependency
      chains will remain on one channel.  When
      ASYNC_TX_DISABLE_CHANNEL_SWITCH=n async_tx_find_channel() may select
      channels that lead to operation chains that need to cross channel
      boundaries using the async_tx channel switch capability.
      Signed-off-by: NDan Williams <dan.j.williams@intel.com>
      138f4c35
    • D
      dmaengine: add fence support · 0403e382
      Dan Williams 提交于
      Some engines optimize operation by reading ahead in the descriptor chain
      such that descriptor2 may start execution before descriptor1 completes.
      If descriptor2 depends on the result from descriptor1 then a fence is
      required (on descriptor2) to disable this optimization.  The async_tx
      api could implicitly identify dependencies via the 'depend_tx'
      parameter, but that would constrain cases where the dependency chain
      only specifies a completion order rather than a data dependency.  So,
      provide an ASYNC_TX_FENCE to explicitly identify data dependencies.
      Signed-off-by: NDan Williams <dan.j.williams@intel.com>
      0403e382
  13. 30 8月, 2009 2 次提交
    • D
      async_tx: add support for asynchronous GF multiplication · b2f46fd8
      Dan Williams 提交于
      [ Based on an original patch by Yuri Tikhonov ]
      
      This adds support for doing asynchronous GF multiplication by adding
      two additional functions to the async_tx API:
      
       async_gen_syndrome() does simultaneous XOR and Galois field
          multiplication of sources.
      
       async_syndrome_val() validates the given source buffers against known P
          and Q values.
      
      When a request is made to run async_pq against more than the hardware
      maximum number of supported sources we need to reuse the previous
      generated P and Q values as sources into the next operation.  Care must
      be taken to remove Q from P' and P from Q'.  For example to perform a 5
      source pq op with hardware that only supports 4 sources at a time the
      following approach is taken:
      
      p, q = PQ(src0, src1, src2, src3, COEF({01}, {02}, {04}, {08}))
      p', q' = PQ(p, q, q, src4, COEF({00}, {01}, {00}, {10}))
      
      p' = p + q + q + src4 = p + src4
      q' = {00}*p + {01}*q + {00}*q + {10}*src4 = q + {10}*src4
      
      Note: 4 is the minimum acceptable maxpq otherwise we punt to
      synchronous-software path.
      
      The DMA_PREP_CONTINUE flag indicates to the driver to reuse p and q as
      sources (in the above manner) and fill the remaining slots up to maxpq
      with the new sources/coefficients.
      
      Note1: Some devices have native support for P+Q continuation and can skip
      this extra work.  Devices with this capability can advertise it with
      dma_set_maxpq.  It is up to each driver how to handle the
      DMA_PREP_CONTINUE flag.
      
      Note2: The api supports disabling the generation of P when generating Q,
      this is ignored by the synchronous path but is implemented by some dma
      devices to save unnecessary writes.  In this case the continuation
      algorithm is simplified to only reuse Q as a source.
      
      Cc: H. Peter Anvin <hpa@zytor.com>
      Cc: David Woodhouse <David.Woodhouse@intel.com>
      Signed-off-by: NYuri Tikhonov <yur@emcraft.com>
      Signed-off-by: NIlya Yanok <yanok@emcraft.com>
      Reviewed-by: NAndre Noll <maan@systemlinux.org>
      Acked-by: NMaciej Sosnowski <maciej.sosnowski@intel.com>
      Signed-off-by: NDan Williams <dan.j.williams@intel.com>
      b2f46fd8
    • D
      async_tx: add sum check flags · ad283ea4
      Dan Williams 提交于
      Replace the flat zero_sum_result with a collection of flags to contain
      the P (xor) zero-sum result, and the soon to be utilized Q (raid6 reed
      solomon syndrome) zero-sum result.  Use the SUM_CHECK_ namespace instead
      of DMA_ since these flags will be used on non-dma-zero-sum enabled
      platforms.
      Reviewed-by: NAndre Noll <maan@systemlinux.org>
      Acked-by: NMaciej Sosnowski <maciej.sosnowski@intel.com>
      Signed-off-by: NDan Williams <dan.j.williams@intel.com>
      ad283ea4
  14. 13 5月, 2009 1 次提交
  15. 09 4月, 2009 1 次提交
  16. 27 3月, 2009 1 次提交
  17. 26 3月, 2009 2 次提交
  18. 19 2月, 2009 1 次提交
  19. 12 2月, 2009 1 次提交
  20. 07 2月, 2009 1 次提交
  21. 20 1月, 2009 2 次提交
  22. 11 1月, 2009 1 次提交
  23. 07 1月, 2009 5 次提交