The remainder of the file uses lower-case for hexadecimal literals, so
change the only odd-one-out occurrence for consistency.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Acked-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The removed barrier isn't needed because writes/reads are strictly ordered
and even if PMC had separate ports for writes, it wouldn't matter since
the hardware logic takes into effect after triggering CPU's power-gating
and at that point all CPU accesses are guaranteed to be completed. That
barrier was copied from the old arch/ code during transition to the soc/
PMC driver and even that the code structure was different back then, the
barrier didn't have a real useful purpose from the start. Lastly, the
tegra_pmc_writel() naturally inserts wmb() because it uses writel(),
and thus this change doesn't actually make any difference in terms of
interacting with hardware. Hence let's remove the barrier to clean up
code a tad.
Signed-off-by: NDmitry Osipenko <digetx@gmail.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

It is possible to get a lockup if kernel decides to enter LP2 cpuidle
from some clk-notifier, in that case CCF's "prepare" mutex is kept locked
and thus clk_get_rate(pclk) blocks on the same mutex with interrupts being
disabled, hanging machine.
Signed-off-by: NDmitry Osipenko <digetx@gmail.com>
Acked-By: NPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add regulators coupler for Tegra30 SoCs that performs voltage balancing
of a coupled regulators and thus provides voltage scaling functionality.

There are 2 coupled regulators on all Tegra30 SoCs: CORE and CPU. The
coupled regulator voltages shall be in a range of 300mV from each other
and CORE voltage shall be higher than the CPU by N mV, where N depends
on the CPU voltage.
Signed-off-by: NDmitry Osipenko <digetx@gmail.com>
Acked-By: NPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add regulators coupler for Tegra20 SoCs that performs voltage balancing
of a coupled regulators and thus provides voltage scaling functionality.

There are 3 coupled regulators on all Tegra20 SoCs: CORE, RTC and CPU.
The CORE and RTC voltages shall be in range of 170mV from each other and
they both shall be higher than the CPU voltage by at least 120mV. This
sounds like it could be handle by a generic voltage balancer, but the CORE
voltage scaling isn't implemented in any of the upstream drivers yet.
It will take quite some time and effort to hook up voltage scaling for
all of the drivers, hence we will use a custom coupler that will manage
the CPU voltage scaling for the starter.
Signed-off-by: NDmitry Osipenko <digetx@gmail.com>
Acked-By: NPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Tegra210 and prior Tegra chips have deep sleep entry and wakeup related
timings which are platform specific that should be configured before
entering into deep sleep.

Below are the timing specific configurations for deep sleep entry and
wakeup.
- Core rail power-on stabilization timer
- OSC clock stabilization timer after SOC rail power is stabilized.
- Core power off time is the minimum wake delay to keep the system
  in deep sleep state irrespective of any quick wake event.

These values depends on the discharge time of regulators and turn OFF
time of the PMIC to allow the complete system to finish entering into
deep sleep state.

These values vary based on the platform design and are specified
through the device tree.

This patch has implementation to configure these timings which are must
to have for proper deep sleep and wakeup operations.
Signed-off-by: NSowjanya Komatineni <skomatineni@nvidia.com>
Reviewed-by: NDmitry Osipenko <digetx@gmail.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

This patch configures polarity of the core power request signal
in PMC control register based on the device tree property.

PMC asserts and de-asserts power request signal based on it polarity
when it need to power-up and power-down the core rail during SC7.
Reviewed-by: NDmitry Osipenko <digetx@gmail.com>
Signed-off-by: NSowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

This patch implements PMC wakeup sequence for Tegra210 and defines the
commonly used RTC alarm wake event.
Signed-off-by: NSowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

This patch allows to create separate irq_set_wake and irq_set_type
implementations for different Tegra designs PMC that has different
wake models which require difference wake registers and different
programming sequence.

AOWAKE model support is available for Tegra186 and Tegra194 only
and it resides within PMC and supports tiered wake architecture.

Tegra210 and prior Tegra designs uses PMC directly to receive wake
events and coordinate the wake sequence.
Reviewed-by: NDmitry Osipenko <digetx@gmail.com>
Signed-off-by: NSowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Typically nvmem cells would be stored in device tree. However, for
compatibility with device trees that don't contain nvmem cell
definitions, register lookups for cells currently used by consumers.
This allows the consumers to use the same API to query cells from the
device tree or using the legacy mechanism.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Create nvmem cells for all the fuses currently used by consumers.
Signed-off-by: NThierry Reding <treding@nvidia.com>

The nvmem framework provides a generic infrastructure and API to access
the type of information stored in fuses such as the Tegra FUSE block.

Implement an nvmem device that can be used to access the information in
a more generic way to decouple consumers from the custom Tegra API and
to add a more formal way of creating the dependency between the FUSE
device and the consumers.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Make sure to also restore the register base address on sysfs
registration failure.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Interrupts that don't have an associated wake event or GPIO wake events
end up with an associate IRQ chip that is NULL and which causes IRQ code
to crash. This is because we don't implicitly set the parent IRQ chip by
allocating the interrupt at the parent. However, there really isn't a
corresponding interrupt at the parent, so we need to work around this by
setting the special no_irq_chip as the IRQ chip for these interrupts.

Fixes: 19906e6b ("soc/tegra: pmc: Add wake event support")
Signed-off-by: NThierry Reding <treding@nvidia.com>

tegra_fuse_readl() can be called from drivers at any time. If this API
is called before tegra_fuse_probe(), we end up enabling the clock before
it is registered. Add a check for the FUSE clock in tegra_fuse_readl()
and propagate any errors.
Signed-off-by: NNagarjuna Kristam <nkristam@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

When booting with ACPI, the Geni Serial Engine is not set as the I2C/SPI
parent and thus, the wrapper (parent device) is unassigned.  This causes
the kernel to crash with a null dereference error.

Link: https://lore.kernel.org/r/20190905082555.15020-1-lee.jones@linaro.org
Fixes: 8bc529b2 ("soc: qcom: geni: Add support for ACPI")
Acked-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: NStephen Boyd <sboyd@kernel.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

TISCI protocol supports for enabling the device either with exclusive
permissions for the requesting host or with sharing across the hosts.
There are certain devices which are exclusive to Linux context and
there are certain devices that are shared across different host contexts.
So add support for getting this information from DT by increasing
the power-domain cells to 2.

For keeping the DT backward compatibility intact, defaulting the
device permissions to set the exclusive flag set. In this case the
power-domain-cells is 1.
Reviewed-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@oracle.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

The move of the IXP4xx SoC drivers exposed their config options on all
platforms.

Fix this by wrapping them inside an ARCH_IXP4XX or COMPILE_TEST block.

Link: https://lore.kernel.org/r/20190823090352.12243-1-linus.walleij@linaro.org
Fixes: fcf2d897 ("ARM: ixp4xx: Move NPE and QMGR to drivers/soc")
Signed-off-by: NGeert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Add support for the General Purpose Amlogic Everything-Else Power controller,
with the first support for G12A and SM1 SoCs dedicated to the VPU, PCIe,
USB, NNA, GE2D and Ethernet Power Domains.
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Reviewed-by: NKevin Hilman <khilman@baylibre.com>
Tested-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

TISCI protocol supports for enabling the device either with exclusive
permissions for the requesting host or with sharing across the hosts.
There are certain devices which are exclusive to Linux context and
there are certain devices that are shared across different host contexts.
So add support for getting this information from DT by increasing
the power-domain cells to 2.

For keeping the DT backward compatibility intact, defaulting the
device permissions to set the exclusive flag set. In this case the
power-domain-cells is 1.
Reviewed-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@oracle.com>

The current code prints 'ret' (thus 0) while it should use 'err'.
Signed-off-by: NGuido Günther <agx@sigxcpu.org>
Reviewed-by: NDaniel Baluta <daniel.baluta@nxp.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

According to the cmdq hardware design, the subsys is u8,
the offset is u16 and the event id is u16.
This patch changes the type of subsys, offset and event id
to the correct type.
Signed-off-by: NBibby Hsieh <bibby.hsieh@mediatek.com>
Reviewed-by: NCK Hu <ck.hu@mediatek.com>
Signed-off-by: NMatthias Brugger <matthias.bgg@gmail.com>

The order of gce instructions is [subsys offset value]
so reorder the parameter of cmdq_pkt_write_mask
and cmdq_pkt_write function.
Signed-off-by: NBibby Hsieh <bibby.hsieh@mediatek.com>
Reviewed-by: NCK Hu <ck.hu@mediatek.com>
Signed-off-by: NMatthias Brugger <matthias.bgg@gmail.com>

ARM Erratum 754322 affects Cortex-A9 revisions r2p* and r3p*.

Automatically enable support code to mitigate the erratum when compiling
a kernel for any of the affected Renesas SoCs:
  - RZ/A1: r3p0,
  - R-Mobile A1: r2p4,
  - R-Car M1A: r2p2-00rel0,
  - R-Car H1: r3p0,
  - SH-Mobile AG5: r2p2.

EMMA Mobile EV2 (r1p3) and RZ/A2 (r4p1) are not affected.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>

ARM Erratum 814220 affects Cortex-A7 revisions r0p2-r0p5.

Automatically enable support code to mitigate the erratum when compiling
a kernel for any of the affected Renesas SoCs:
  - R-Mobile APE6: r0p2,
  - RZ/G1E: r0p5,
  - RZ/G1C: r0p5,
  - R-Car H2: r0p3,
  - R-Car E2: r0p5,
  - RZ/N1: r0p5.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>

Currently the R-Mobile "always-on" PM Domain is implemented by returning
-EBUSY from the generic_pm_domain.power_off() callback, and doing
nothing in the generic_pm_domain.power_on() callback.  However, this
means the PM Domain core code is not aware of the semantics of this
special domain, leading to boot warnings like the following on
SH/R-Mobile SoCs:

    sh_cmt e6130000.timer: PM domain c5 will not be powered off

Fix this by making the always-on nature of the domain explicit instead,
by setting the GENPD_FLAG_ALWAYS_ON flag.  This removes the need for the
domain to provide power control callbacks.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>
Reviewed-by: NUlf Hansson <ulf.hansson@linaro.org>

The chipid driver uses the MFD syscon API but it was not covered
properly in Kconfig.
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>

In commit 40d8aff6 ("soc: samsung: chipid: Convert exynos-chipid
driver to use the regmap API") of_find_compatible_node() call was
substituted with syscon_regmap_lookup_by_compatible() but also an error
log was added for case where lookup fails. On multiplatform the lookup
will always fail on any non-samsung device so the log is incorrect.
Remove the error log and just return an error code from
syscon_regmap_lookup_by_compatible() which internally calls
of_find_compatible_node().
Reported-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>

Add AOSS QMP support for SM8150 and SC7180 SoCs.
Reviewed-by: NVinod Koul <vkoul@kernel.org>
Tested-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NSibi Sankar <sibis@codeaurora.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>

Update max processor count to reflect the number of
co-processors on SC7180 SoCs.
Reviewed-by: NVinod Koul <vkoul@kernel.org>
Tested-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NSibi Sankar <sibis@codeaurora.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>

The variable np in function meson_gx_socinfo_init takes the return value
of of_find_compatible_node, which gets a node but does not put it. If
this node is not put it may cause a memory leak. Hence put np after its
usefulness has been exhausted.
Issue found with Coccinelle.
Signed-off-by: NNishka Dasgupta <nishkadg.linux@gmail.com>
Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com>
Fixes: a9daaba2 ("soc: Add Amlogic SoC Information driver")
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Add the clk-measurer clocks IDs for the Amlogic SM1 SoC family.
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Add the SoC IDs for the S905X3 Amlogic SM1 SoC.
Reviewed-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Currently when the call to product_id_to_soc_id fails there
is a memory leak of soc_dev_attr->revision and soc_dev_attr
on the error return path.  Fix this by adding a common error
return path that frees there obects and use this for two
error return paths.

Addresses-Coverity: ("Resource leak")
Fixes: 3253b7b7 ("soc: samsung: Add exynos chipid driver support")
Signed-off-by: NColin Ian King <colin.king@canonical.com>
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>

As of commit 980532a5 ("soc: renesas: rcar-sysc: Use
GENPD_FLAG_ALWAYS_ON"), the local variable "gov" is assigned just once,
so it can be eliminated.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>
Reviewed-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>

The local variable np in function rcar_sysc_pd_init takes the return
value of of_find_matching_node_and_match(), which gets a node but does
not put it.  If np is not put before the function returns, it may cause
a memory leak.

Hence, remove the return statement that does not immediately follow a
putting of np.  Replace it with a goto pointing to a pre-existing label
that first puts np and then returns the required value.

Issue found with Coccinelle.

Fixes: afa6f53d ("soc: renesas: rcar-sysc: Add support for fixing up power area tables")
Signed-off-by: NNishka Dasgupta <nishkadg.linux@gmail.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Starting with commit 72175d4e ("driver core: Make driver core
own stateful device links") stateful device links are owned by the
driver core and should not be explicitly removed on device unbind.
Delete all device_link_remove appearances from the dpio driver.
Signed-off-by: NIoana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: NLi Yang <leoyang.li@nxp.com>

Adding compatible string "ls1028a-dcfg" to initialize guts driver
for ls1028 and SoC die attribute definition for LS1028A
Signed-off-by: NYinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: NLi Yang <leoyang.li@nxp.com>

When using the reserved memory node in the device tree there are
two options - dynamic or static. If a dynamic allocation was
selected (where the kernel selects the address for the allocation)
convert it to a static allocation by inserting the reg property.
This will ensure the same memory is reused after a kexec()
Signed-off-by: NRoy Pledge <roy.pledge@nxp.com>
Signed-off-by: NLi Yang <leoyang.li@nxp.com>

When shutting down a FQ on a dedicated channel only the
SW portal associated with that channel can dequeue from it.
Make sure the correct portal is use.
Signed-off-by: NRoy Pledge <roy.pledge@nxp.com>
Signed-off-by: NLi Yang <leoyang.li@nxp.com>