1. 12 7月, 2015 3 次提交
  2. 06 6月, 2015 1 次提交
  3. 25 4月, 2015 1 次提交
  4. 09 4月, 2015 1 次提交
  5. 26 3月, 2015 2 次提交
  6. 15 3月, 2015 3 次提交
  7. 08 3月, 2015 1 次提交
  8. 26 1月, 2015 1 次提交
  9. 26 11月, 2014 2 次提交
  10. 22 10月, 2014 1 次提交
    • L
      ARM: realview: basic device tree implementation · fa6e2eec
      Linus Walleij 提交于
      This implements basic device tree boot support for the RealView
      platforms, with a basic device tree for ARM PB1176 as an example.
      
      The implementation is done with a new DT-specific board file
      using only pre-existing bindings for the basic IRQ, timer and
      serial port drivers. A new compatible type is added to the GIC
      for the ARM1176.
      
      This implementation uses the MFD syscon handle from day one to
      access the system controller registers, and register the devices
      using the SoC bus.
      
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: Rob Herring <robh@kernel.org>
      Acked-by: NJason Cooper <jason@lakedaemon.net>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      fa6e2eec
  11. 19 9月, 2014 1 次提交
  12. 03 9月, 2014 2 次提交
  13. 27 8月, 2014 1 次提交
  14. 19 8月, 2014 2 次提交
  15. 18 7月, 2014 1 次提交
  16. 17 7月, 2014 1 次提交
  17. 09 7月, 2014 2 次提交
  18. 19 6月, 2014 1 次提交
  19. 19 5月, 2014 1 次提交
  20. 18 4月, 2014 1 次提交
  21. 12 3月, 2014 1 次提交
  22. 06 3月, 2014 1 次提交
  23. 26 2月, 2014 1 次提交
  24. 05 2月, 2014 1 次提交
    • S
      DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs · 006e983b
      Sricharan R 提交于
      In some socs the gic can be preceded by a crossbar IP which
      routes the peripheral interrupts to the gic inputs. The peripheral
      interrupts are associated with a fixed crossbar input line and the
      crossbar routes that to one of the free gic input line.
      
      The DT entries for peripherals provides the fixed crossbar input line
      as its interrupt number and the mapping code should associate this with
      a free gic input line. This patch adds the support inside the gic irqchip
      to handle such routable irqs. The routable irqs are registered in a linear
      domain. The registered routable domain's callback should be implemented
      to get a free irq and to configure the IP to route it.
      
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Linus Walleij <linus.walleij@linaro.org>
      Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
      Cc: Russell King <linux@arm.linux.org.uk>
      Cc: Tony Lindgren <tony@atomide.com>
      Cc: Rajendra Nayak <rnayak@ti.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Grant Likely <grant.likely@linaro.org>
      Cc: Rob Herring <rob.herring@calxeda.com>
      Signed-off-by: NSricharan R <r.sricharan@ti.com>
      Reviewed-by: NThomas Gleixner <tglx@linutronix.de>
      Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
      Acked-by: NLinus Walleij <linus.walleij@linaro.org>
      006e983b
  25. 28 11月, 2013 1 次提交
  26. 24 9月, 2013 2 次提交
  27. 29 8月, 2013 1 次提交
    • N
      drivers: irq-chip: irq-gic: introduce gic_cpu_if_down() · 10d9eb8a
      Nicolas Pitre 提交于
      When processors are about to hit low power states, the assertion of
      standbywfi signal, triggered by the wfi instruction, is essential to
      entering low power modes. If an IRQ is pending on the processor at the
      time wfi is issued, the wfi instruction completes and the processor
      restarts execution without asserting the standbywfi signal. Depending
      on the platform power controller HW this behaviour can be acceptable or
      not; if this behaviour must be prevented software should be provided
      with a way to disable the routing of interrupts to the core IRQ pins.
      
      On systems where raw GIC distributor interrupts are connected to the power
      controller as wake-up events (hence the power controller still senses
      IRQs and can wake up cores upon IRQ pending), the GIC CPU interface can
      be disabled on power down, so that the GIC CPU IF output is gated and wfi
      cannot complete, thereby preventing the standbywfi issue.
      
      This patch adds a simple function to the GIC driver that allows to
      disable the GIC CPU IF from power down procedures.
      Signed-off-by: NNicolas Pitre <nico@linaro.org>
      Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      [rewrote commit log]
      Signed-off-by: NOlof Johansson <olof@lixom.net>
      10d9eb8a
  28. 30 7月, 2013 2 次提交
    • N
      ARM: bL_switcher: do not hardcode GIC IDs in the code · ed96762e
      Nicolas Pitre 提交于
      Currently, GIC IDs are hardcoded making the code dependent on the 4+4 b.L
      configuration.  Let's allow for GIC IDs to be discovered upon switcher
      initialization to support other b.L configurations such as the 1+1 one,
      or 2+3 as on the VExpress TC2.
      Signed-off-by: NNicolas Pitre <nico@linaro.org>
      ed96762e
    • N
      ARM: gic: add CPU migration support · 1a6b69b6
      Nicolas Pitre 提交于
      This is required by the big.LITTLE switcher code.
      
      The gic_migrate_target() changes the CPU interface mapping for the
      current CPU to redirect SGIs to the specified interface, and it also
      updates the target CPU for each interrupts to that CPU interface
      if they were targeting the current interface.  Finally, pending
      SGIs for the current CPU are forwarded to the new interface.
      
      Because Linux does not use it, the SGI source information for the
      forwarded SGIs is not preserved.  Neither is the source information
      for the SGIs sent by the current CPU to other CPUs adjusted to match
      the new CPU interface mapping.  The required registers are banked so
      only the target CPU could do it.
      Signed-off-by: NNicolas Pitre <nico@linaro.org>
      1a6b69b6
  29. 15 7月, 2013 1 次提交
    • P
      clocksource+irqchip: delete __cpuinit usage from all related files · 8c37bb3a
      Paul Gortmaker 提交于
      The __cpuinit type of throwaway sections might have made sense
      some time ago when RAM was more constrained, but now the savings
      do not offset the cost and complications.  For example, the fix in
      commit 5e427ec2 ("x86: Fix bit corruption at CPU resume time")
      is a good example of the nasty type of bugs that can be created
      with improper use of the various __init prefixes.
      
      After a discussion on LKML[1] it was decided that cpuinit should go
      the way of devinit and be phased out.  Once all the users are gone,
      we can then finally remove the macros themselves from linux/init.h.
      
      This removes all the drivers/clocksource and drivers/irqchip uses of
      the __cpuinit macros from all C files.
      
      [1] https://lkml.org/lkml/2013/5/20/589
      
      Cc: John Stultz <john.stultz@linaro.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Acked-by: NThomas Gleixner <tglx@linutronix.de>
      Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
      8c37bb3a