1. 04 8月, 2016 9 次提交
  2. 03 8月, 2016 5 次提交
  3. 26 7月, 2016 1 次提交
  4. 20 7月, 2016 1 次提交
  5. 08 7月, 2016 1 次提交
  6. 05 7月, 2016 2 次提交
  7. 04 7月, 2016 1 次提交
  8. 27 6月, 2016 1 次提交
  9. 24 6月, 2016 1 次提交
  10. 18 6月, 2016 1 次提交
  11. 13 6月, 2016 1 次提交
  12. 23 5月, 2016 1 次提交
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  14. 14 5月, 2016 2 次提交
  15. 11 5月, 2016 1 次提交
  16. 10 5月, 2016 1 次提交
    • V
      drm/i915: Re-enable GGTT earlier during resume on pre-gen6 platforms · ac840ae5
      Ville Syrjälä 提交于
      Move the intel_enable_gtt() call to happen before we touch the GTT
      during resume. Right now it's done way too late. Before
      commit ebb7c78d ("agp/intel-gtt: Only register fake agp driver for gen1")
      it was actually done earlier on account of also getting called from
      the resume hook of the fake agp driver. With the fake agp driver
      no longer getting registered we must move the call up.
      
      The symptoms I've seen on my 830 machine include lowmem corruption,
      other kinds of memory corruption, and straight up hung machine during
      or just after resume. Not really sure what causes the memory corruption,
      but so far I've not seen any with this fix.
      
      I think we shouldn't really need to call this during init, but we have
      been doing that so I've decided to keep the call. However moving that
      call earlier could be prudent as well. Doing it right after the
      intel-gtt probe seems appropriate.
      
      Also tested this on 946gz,elk,ilk and all seemed quite happy with
      this change.
      
      v2: Reorder init_hw vs. enable_hw functions (Chris)
      
      Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
      Cc: drm-intel-fixes@lists.freedesktop.org
      Fixes: ebb7c78d ("agp/intel-gtt: Only register fake agp driver for gen1")
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1462559755-353-1-git-send-email-ville.syrjala@linux.intel.comReviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      ac840ae5
  17. 09 5月, 2016 1 次提交
  18. 05 5月, 2016 1 次提交
  19. 29 4月, 2016 1 次提交
  20. 28 4月, 2016 3 次提交
  21. 27 4月, 2016 1 次提交
  22. 22 4月, 2016 1 次提交
  23. 19 4月, 2016 1 次提交
  24. 14 4月, 2016 1 次提交
    • M
      drm/i915: Store and use edram capabilities · 3accaf7e
      Mika Kuoppala 提交于
      Store the edram capabilities instead of only the size of
      edram. This is preparatory patch to allow edram size calculation
      based on edram capability bits for gen9+. With gen9 the
      edram is behind llc and is a separate entity. With hsw/bdw
      it was more of a victim cache for LLC so the name 'eLLC' might
      be warranted. Regardless, rename all mentions of eLLC to EDRAM to
      clear the confusion.
      
      v2: return bytes for edram size (Chris)
          s/eLLC/eDRAM in output if we are gen > 8
      
      v3: rebase, INTEL_GEN (Chris)
      Signed-off-by: NMika Kuoppala <mika.kuoppala@intel.com>
      Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      3accaf7e