- 20 12月, 2017 1 次提交
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由 Sean Nyekjaer 提交于
Signed-off-by: NSean Nyekjaer <sean.nyekjaer@prevas.dk> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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- 13 12月, 2017 4 次提交
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由 Hou Zhiqiang 提交于
Add this API to restore the status of SPI flash chip to the default such as addressing mode, whenever detach the driver from device or reboot the system. Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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由 Aaron Sierra 提交于
Previously, the lock and unlock functions returned success even if the BP bits were not actually updated in the status register due to hardware write protection. Introduce write_sr_and_check() to write and read back the status register to ensure the desired BP bits are actually set as requested. Signed-off-by: NJoe Schultz <jschultz@xes-inc.com> Signed-off-by: NAaron Sierra <asierra@xes-inc.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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由 Bean Huo (beanhuo) 提交于
For Micron spi nor device, when erase/program operation fails, especially the failure results from intending to modify protected space, spi-nor upper layers still get the return which shows the operation succeeds. This is because current spi_nor_fsr_ready() only uses FSR bit.7 (flag status register) to check device whether ready. This patch fixes this issue by checking relevant error bits in FSR. The FSR is a powerful tool to investigate the status of device, checking information regarding what the memory is actually doing and detecting possible error conditions. Signed-off-by: Nbeanhuo <beanhuo@micron.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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由 Angelo Dureghello 提交于
Add support for ISSI is25lp128 spi nor flash. Signed-off-by: NAngelo Dureghello <angelo@sysam.it> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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- 02 11月, 2017 1 次提交
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由 Greg Kroah-Hartman 提交于
Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: NKate Stewart <kstewart@linuxfoundation.org> Reviewed-by: NPhilippe Ombredanne <pombredanne@nexb.com> Reviewed-by: NThomas Gleixner <tglx@linutronix.de> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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- 30 10月, 2017 6 次提交
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This patch adds Intel Lewisburg PCH SPI serial flash controller super SKU PCI ID. Signed-off-by: NKuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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由 Philipp Puschmann 提交于
Add Everspin mr25h128 16KB MRAM to the list of supported chips. Signed-off-by: NPhilipp Puschmann <pp@emlix.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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由 Roman Yeryomin 提交于
Signed-off-by: NRoman Yeryomin <roman@advem.lv> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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由 Ludovic Barre 提交于
When memory-mapped mode is used, a prefetching mechanism fully managed by the hardware allows to optimize the read from external the QSPI memory. A 32-bytes FIFO is used for prefetching. When the limit of flash size - fifo size is reached the prefetching mechanism tries to read outside the fsize. The stm32 quadspi hardware become busy and should be aborted. Signed-off-by: NLudovic Barre <ludovic.barre@st.com> Reported-by: NBruno Herrera <bruherrera@gmail.com> Tested-by: NBruno Herrera <bruherrera@gmail.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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由 Ludovic Barre 提交于
-Change the license text with long template. -Change Copyright to STMicroelectronics. Signed-off-by: NLudovic Barre <ludovic.barre@st.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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由 Geert Uytterhoeven 提交于
With gcc 4.1.2: drivers/mtd/spi-nor/stm32-quadspi.c: In function ‘stm32_qspi_tx_poll’: drivers/mtd/spi-nor/stm32-quadspi.c:230: warning: ‘ret’ may be used uninitialized in this function Indeed, if stm32_qspi_cmd.len is zero, ret will be uninitialized. This length is passed from outside the driver using the spi_nor.{read,write}{,_reg}() callbacks. Several functions in drivers/mtd/spi-nor/spi-nor.c (e.g. write_enable(), write_disable(), and erase_chip()) call spi_nor.write_reg() with a zero length. Fix this by returning an explicit zero on success. Fixes: 0d43d7ab ("mtd: spi-nor: add driver for STM32 quad spi flash controller") Signed-off-by: NGeert Uytterhoeven <geert@linux-m68k.org> Acked-by: NLudovic Barre <ludovic.barre@st.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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- 25 10月, 2017 2 次提交
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由 Bin Meng 提交于
The idea to have the intel-spi driver dependent on EXPERT was exactly because we did not want ordinary users playing with the device and inadvertently overwrite their BIOSes (if it is not protected). This seems to be superfluous hence remove it. Suggested-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com> Acked-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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由 Guochun Mao 提交于
Abstract functions of clock setting, to avoid duplicated code, these functions been used in new feature. Implement suspend/resume functions. Signed-off-by: NGuochun Mao <guochun.mao@mediatek.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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- 23 10月, 2017 1 次提交
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由 Neil Armstrong 提交于
Add JEDEC entry for the Winbond w25q16fw/w25q16dw with similar flags and format than the Winbond w25q32dw entry. Tested on a Khadas VIM2 SBC board with an Amlogic S912 SoC. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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- 18 10月, 2017 4 次提交
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由 Vignesh R 提交于
Add pm_runtime* calls to cadence-quadspi driver. This is required to switch on QSPI power domain on TI 66AK2G SoC during probe. Signed-off-by: NVignesh R <vigneshr@ti.com> Acked-by: NMarek Vasut <marek.vasut@gmail.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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由 Vignesh R 提交于
Fix the reversed goto labels, so that we disable cqspi controller only if its enabled previously. This is a minor cleanup. Signed-off-by: NVignesh R <vigneshr@ti.com> Acked-by: NMarek Vasut <marek.vasut@gmail.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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由 Vignesh R 提交于
Cadence QSPI IP has a adapted loop-back circuit which can be enabled by setting BYPASS field to 0 in READCAPTURE register. It enables use of QSPI return clock to latch the data rather than the internal QSPI reference clock. For high speed operations, adapted loop-back circuit using QSPI return clock helps to increase data valid window. Based on DT parameter cdns,rclk-en enable adapted loop-back circuit for boards which do have QSPI return clock provided. This patch also modifies cqspi_readdata_capture() function's bypass parameter to bool to match how its used in the function. Signed-off-by: NVignesh R <vigneshr@ti.com> Acked-by: NMarek Vasut <marek.vasut@gmail.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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由 Vignesh R 提交于
As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access Controller programming sequence, a delay equal to couple of QSPI master clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and writing data to the flash. Introduce a quirk flag CQSPI_NEEDS_WR_DELAY to handle this and set this flag for TI 66AK2G SoC. [1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdfSigned-off-by: NVignesh R <vigneshr@ti.com> Acked-by: NMarek Vasut <marek.vasut@gmail.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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- 11 10月, 2017 18 次提交
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由 Bin Meng 提交于
According to the datasheet, the HW sequencer has a predefined list of opcodes, with only the erase opcode being programmable in LVSCC and UVSCC registers. If these registers don't contain a valid erase opcode (eg: BIOS does not program it), erase cannot be done using the HW sequencer, even though the erase operation does not report any error, the flash remains not erased. If such register setting is detected, let's fall back to use the SW sequencer to erase instead. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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由 Bin Meng 提交于
The ispi->swseq is used for register access. Let's rename it to swseq_reg to better describe its usage. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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由 Bin Meng 提交于
There is no code that alters the HSFSTS register content in between in intel_spi_write(). Remove the unnecessary RW to save some cycles. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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由 Bin Meng 提交于
At present the driver relies on valid OPMENU0/OPMENU1 register values that are programmed by BIOS to function correctly. However in a real world it's absolutely legitimate for a bootloader to leave these two registers untouched. Intel FSP for Baytrail exactly does like this. When we are booting from any Intel FSP based bootloaders like U-Boot, the driver refuses to work. We can of course program various flash opcodes in the OPMENU0/OPMENU1 registers, and such workaround can be added in either the bootloader codes, or the kernel driver itself. But a graceful solution would be to update the kernel driver to remove such limitation of OPMENU0/1 register dependency. The SPI controller settings are not locked under such configuration. So we can first check the controller locking status, and if it is not locked that means the driver job can be fulfilled by using a chosen OPMENU index to set up the flash opcode every time. While we are here, the missing 'Atomic Cycle Sequence' handling in the SW sequencer codes is also added. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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由 Bin Meng 提交于
So far intel_spi_write() uses the HW sequencer to do the write. But the HW sequencer register HSFSTS_CTL does not have such a field for 'Atomic Cycle Sequence', remove it. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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由 Bin Meng 提交于
Baytrail/Lynx Point SPI controller's HW sequencer only supports basic operations. This is determined by the chipset design, however current codes try to use register values in OPMENU0/OPMENU1 to see whether SW sequencer should be used, which is wrong. In fact OPMENU0/OPMENU1 can remain unprogrammed by some bootloaders. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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由 Bin Meng 提交于
Intel SPI controller only has a 64 bytes FIFO. This adds a sanity check before triggering any HW/SW sequencer work. Additionally for the SW sequencer, if given data length is zero, we should not mark the 'Data Cycle' bit. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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由 Bin Meng 提交于
There are two bugs in current intel_spi_sw_cycle(): - The 'data byte count' field should be the number of bytes transferred minus 1 - SSFSTS_CTL is the offset from ispi->sregs, not ispi->base Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Cc: <stable@vger.kernel.org> # v4.11+ Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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由 Bin Meng 提交于
intel_spi_hw_cycle() and intel_spi_sw_cycle() don't use the parameter 'buf' at all. Remove it. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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由 Bin Meng 提交于
The number of protected range registers is not the same on BYT/LPT/ BXT. GPR0 only exists on Apollo Lake and its offset is reserved on other platforms. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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由 Mika Westerberg 提交于
Intel Cedar Fork has the same SPI serial flash controller than Intel Denverton. Add the Intel Cedar Fork PCI ID to the driver list of supported devices. Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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由 Mika Westerberg 提交于
Intel Lewisburg chipset exposes the SPI serial flash controller as a PCI device in the same way than Intel Denverton. Add Intel Lewisburg SPI serial flash PCI ID to the driver list of supported devices. Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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由 Klaus Goger 提交于
Tested against GD25LQ32D but the GD25LQ32C datasheet seems to be identically feature-wise. Therefore dropping the suffix as it's probably only indicating the die revision. Signed-off-by: NKlaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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由 Andy Yan 提交于
Add support for GD25Q256, a 32MiB SPI Nor flash from GigaDevice. Signed-off-by: NAndy Yan <andy.yan@rock-chips.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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由 Andy Yan 提交于
Some manufacturers may use different bit to set QE on different memories. The GD25Q256 from GigaDevice is an example, which uses S6(bit 6 of the Status Register-1) to set QE, which is different with other supported memories from GigaDevice that use S9(bit 1 of the Status Register-2). This makes it is impossible to select the quad enable method by distinguishing the MFR. This patch introduce a quad_enable function which can be set per memory in the flash_info list table. Signed-off-by: NAndy Yan <andy.yan@rock-chips.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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由 Thor Thayer 提交于
Allow ARM64 support for the Cadence QSPI interface by adding ARM64 as a dependency. Signed-off-by: NThor Thayer <thor.thayer@linux.intel.com> Reviewed-by: NMarek Vasut <marek.vasut@gmail.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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由 Kamal Dasu 提交于
Implemented and populated spi-nor mtd PM handlers for resume ops. spi-nor resume op re-initializes spi-nor flash to its probed state by calling the newly implemented spi_nor_init() function. Signed-off-by: NKamal Dasu <kdasu.kdev@gmail.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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由 Kamal Dasu 提交于
This patch extracts some chunks from spi_nor_init_params and spi_nor_scan() and moves them into a new spi_nor_init() function. Indeed, spi_nor_init() regroups all the required SPI flash commands to be sent to the SPI flash memory before performing any runtime operations (Fast Read, Page Program, Sector Erase, ...). Hence spi_nor_init(): 1) removes the flash protection if applicable for certain vendors. 2) sets the Quad Enable bit, if needed, before using Quad SPI protocols. 3) makes the memory enter its (stateful) 4-byte address mode, if needed, for SPI flash memory > 128Mbits not supporting the 4-byte address instruction set. spi_nor_scan() now ends by calling spi_nor_init() once the probe phase has completed. Further patches could also use spi_nor_init() to implement the mtd->_resume() handler for the spi-nor framework. Signed-off-by: NKamal Dasu <kdasu.kdev@gmail.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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- 10 10月, 2017 1 次提交
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由 Richard Weinberger 提交于
header.minor is of type u8 and cannot be negative. Detected by CoverityScan CID#1417858 ("Integer handling issues") Fixes: f384b352 ("mtd: spi-nor: parse Serial Flash Discoverable Parameters (SFDP) tables") Signed-off-by: NRichard Weinberger <richard@nod.at> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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- 18 9月, 2017 2 次提交
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由 Cyrille Pitchen 提交于
spi_nor_read_sfdp() calls nor->read() to read the SFDP data. When the m25p80 driver is used (pretty common case), nor->read() is then implemented by the m25p80_read() function, which is likely to initialize a 'struct spi_transfer' from its buf argument before appending this structure inside the 'struct spi_message' argument of spi_sync(). Besides the SPI sub-system states that both .tx_buf and .rx_buf members of 'struct spi_transfer' must point into dma-safe memory. However, two of the three calls of spi_nor_read_sfdp() were given pointers to stack allocated memory as buf argument, hence not in a dma-safe area. Hopefully, the third and last call of spi_nor_read_sfdp() was already given a kmalloc'ed buffer argument, hence dma-safe. So this patch fixes this issue by introducing a spi_nor_read_sfdp_dma_unsafe() function which simply wraps the existing spi_nor_read_sfdp() function and uses some kmalloc'ed memory as a bounce buffer. Fixes: f384b352 ("mtd: spi-nor: parse Serial Flash Discoverable Parameters (SFDP) tables") Reported-by: NGeert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Boris Brezillon 提交于
One field of the flash parameter table contains information about the flash device size. Most of the time the data extracted from this field is valid, but sometimes the BFPT section of the SFDP table is corrupted or invalid and this field is set to 0xffffffff, thus resulting in an integer overflow when setting params->size. Since NOR devices are anayway always smaller than 2^64 bytes, we can easily stop the BFPT parsing if the size reported in this table is invalid. Fixes: f384b352 ("mtd: spi-nor: parse Serial Flash Discoverable Parameters (SFDP) tables") Reported-by: NGeert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com> Tested-by: NGeert Uytterhoeven <geert+renesas@glider.be> Acked-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.com>
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