the soft gpu metrics is not asic related data structure.
unify them to reduce duplicate code.
Signed-off-by: NKevin Wang <kevin1.wang@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Add functions to support enable/disable rom clock gating and get rom
clock gating status.
Signed-off-by: NLikun Gao <Likun.Gao@amd.com>
Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Switch to smuio callbacks: use smuio v11_0_6 callbacks for
Sienna_cichlid and forward ASIC, use smuio v11_0 callbacks for the
other NV family ASIC.
Signed-off-by: NLikun Gao <Likun.Gao@amd.com>
Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Implement smuio v11_0_6 callbacks which will used by Sienna_Cichlid and
forward ASIC.
Signed-off-by: NLikun Gao <Likun.Gao@amd.com>
Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NLikun Gao <Likun.Gao@amd.com>
Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Support to program ASPM and LTR for Sienna Cichlid and forward ASIC.
Disable ASPM for Sienna Cichlid and forward ASIC by default.
Signed-off-by: NLikun Gao <Likun.Gao@amd.com>
Reviewed-by: NKenneth Feng <kenneth.feng@amd.com>
Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Enable DCS

V1: Enable Async DCS.
V2: Add the ppfeaturemask bit to enable from the modprobe parameter.
V3:
1. add the flag to skip APU support.
2. remove the hunk for workload selection since
it doesn't impact the function.
Signed-off-by: NKenneth Feng <kenneth.feng@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

The hw interface changed on arcturus so the old numbering
scheme doesn't work.
Acked-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Align with Vangogh.

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1467Acked-by: NNirmoy Das <nirmoy.das@amd.com>
Reviewed-by: NEvan Quan <evan.quan@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Instead of caching the value during amdgpu_device_init, just call the
function directly. This avoids issues where the unique_id hasn't been
saved by the time that KFD's topology snapshot is done (e.g. Arcturus).

KFD's topology information from the amdgpu_device was initially cached
at KFD initialization due to amdkfd and amdgpu being separate modules.
Now that they are combined together, we can directly call the functions
that we need and avoid this unnecessary duplication and complexity.

As a side-effect of this change, we also remove unique_id=0 for CPUs,
which is obviously not unique.

v2: Drop previous patch printing unique_id in hex
Signed-off-by: NKent Russell <kent.russell@amd.com>
Reviewed-by: NFelix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

The power limit and clock ragne are different in AC mode and DC mode.
Firmware does the setting after this feature is enabled.
Signed-off-by: NKenneth Feng <kenneth.feng@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Enable gfx wave limiting for gfx jobs before pushing high priority
compute jobs so that high priority compute jobs gets more resources
to finish early.

v2: use ring priority instead of job priority.
Signed-off-by: NNirmoy Das <nirmoy.das@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Wave limiting can be use to load balance high priority
compute jobs along with gfx jobs. When enabled, this will reserve
~75% of waves for compute jobs.

We do not need this from gfx10 onwards because >=gfx10 has
asynchronous compute tunneling to replace wave limit requirement.
Signed-off-by: NNirmoy Das <nirmoy.das@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

For high priority compute to work properly we need to enable
wave limiting on gfx pipe. Wave limiting is done through writing
into mmSPI_WCL_PIPE_PERCENT_GFX register. Enable only one high
priority compute queue to avoid race condition between multiple
high priority compute queues writing that register simultaneously.
Signed-off-by: NNirmoy Das <nirmoy.das@amd.com>
Acked-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This patch consist of below related changes:

1 Rename ring->priority to ring->hw_prio.
2 Assign correct hardware ring priority.
3 Remove ring->priority_mutex as ring priority remains unchanged
  after initialization.
4 Remove unused ring->num_jobs.

v3: remove ring->num_jobs.
v2: remove ring->priority_mutex.

Fixes: 33abcb1f ("drm/amdgpu: set compute queue priority at mqd_init")
Signed-off-by: NNirmoy Das <nirmoy.das@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
The dm struct is only being used if DCN config is defined and this
causes a unused variable warning if DCN option is not set.

[How]
Remove the compile flag so the variable is used (there also seems to be
a duplicate guard due to a bad rebase) so remove the outer guard to fix
the warning.

Fixes this warning
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c: In function 'dm_set_vblank':
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:5380:33: warning: unused variable 'dm' [-Wunused-variable]

Fixes: 98ab5f35 ("drm/amd/display: Fix deadlock during gpu reset v3")
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Cc: Stephen Rothwell <sfr@canb.auug.org.au>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This reverts commit 4c3a3292.

Bhawan's fix is better (less ifdefs), so revert this and apply Bhawan's.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

After all users of the 'dm' warnings got hidden in an #ifdef,
the compiler started warning about it being unused:

drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5380:33: error: unused variable 'dm' [-Werror,-Wunused-variable]

Add another such #ifdef.

Fixes: 98ab5f35 ("drm/amd/display: Fix deadlock during gpu reset v3")
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Reviewed-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NDave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210125124849.102037-1-arnd@kernel.org

Merge tag 'amd-drm-next-5.12-2021-02-03' of https://gitlab.freedesktop.org/agd5f/linux into drm-next

amd-drm-next-5.12-2021-02-03:

amdgpu:
- Display fixes and cleanups
- Vangogh fixes
- Fix possible race when there are timeouts on two rings
- SR-IOV fixes
- Add missing license
- DCE 10/12 bpc fixes
- Display MALL fixes
- Fix SMU user preference settings persistence
- Fix retry in gem allocate
- Add new PCI DID
- Fix for manual fan speed control on cards where it was problematic
- Fix regression in pinning GTT
- Misc display fixes
- Misc code cleanups

amdkfd:
- Fix config handling
- Fix regression in buffer free

From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210204045717.3823-1-alexander.deucher@amd.comSigned-off-by: NDave Airlie <airlied@redhat.com>

Merge tag 'mediatek-drm-next-5.12' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-next

Mediatek DRM Next for Linux 5.12

1. Decouple Mediatek DRM sub driver
2. Share mtk mutex driver for both DRM and MDP
3. Add support for SoC MT8183
Signed-off-by: NDave Airlie <airlied@redhat.com>

From: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20210204151750.7550-1-chunkuang.hu@kernel.org

Add matrix_bits and coeffs_precision to ccorr private data:
- matrix bits of mt8183 is 10
- matrix bits of mt8192 is 11
Signed-off-by: NYongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: NHsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: NCK Hu <ck.hu@mediatek.com>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>

Fix setting to follow hardware datasheet. The original error setting
affects mt8192 display.
Signed-off-by: NYongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: NHsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: NCK Hu <ck.hu@mediatek.com>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>

ccorr ctm matrix bits will be different in mt8192.
Signed-off-by: NYongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: NHsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: NCK Hu <ck.hu@mediatek.com>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>

Enable dither function to improve the display quality.
Signed-off-by: NYongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: NHsin-Yi Wang <hsinyi@chromium.org>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>

Enable OVL_LAYER_SMI_ID_EN for multi-layer usecase, without this patch,
ovl will hang up when more than 1 layer enabled.
Signed-off-by: NYongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: NHsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: NCK Hu <ck.hu@mediatek.com>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>

1. Add ovl private data
2. Add rdma private data
3. Add gamma privte data
4. Add main and external path module for crtc create
Signed-off-by: NYongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: NHsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: NCK Hu <ck.hu@mediatek.com>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>

Not all SoC has dither function in gamma module.
Add private data to control this function setting.
Signed-off-by: NYongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: NHsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: NCK Hu <ck.hu@mediatek.com>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>

mt8183 gamma module will different with mt8173,
so separate gamma for adding private data.
Signed-off-by: NYongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: NHsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: NCK Hu <ck.hu@mediatek.com>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>

Current implementation of mtk_dither_set() cast dev data to
struct mtk_ddp_comp_dev. But other devices with different dev data
would also call this function.

Separate necessary parameters out so other device components (dither,
gamma) can call this function.
Signed-off-by: NHsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: NCK Hu <ck.hu@mediatek.com>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>

mtk mutex is used by DRM and MDP driver, and its function is SoC-specific,
so move it to soc folder.
Signed-off-by: NCK Hu <ck.hu@mediatek.com>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>
Acked-by: NMatthias Brugger <matthias.bgg@gmail.com>

Moving mutex resource management from client driver to  mutex driver
could prevent client drivers negotiating for resource management.
Signed-off-by: NCK Hu <ck.hu@mediatek.com>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>

mtk mutex is used by both drm and mdp driver, so change disp/ddp term to
mutex to show that it's a common driver for drm and mdp.
Signed-off-by: NCK Hu <ck.hu@mediatek.com>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>

After mmsys routing function is moved out of mtk_drm_ddp.c, mtk_drm_ddp.c
has only mtk mutex function, so rename it to match the function in it.
Signed-off-by: NCK Hu <ck.hu@mediatek.com>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>

Those file includings are useless, so remove them.
Signed-off-by: NCK Hu <ck.hu@mediatek.com>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>

Get the fifo size from device tree
because each rdma in the same SoC may have different fifo size
Signed-off-by: NYongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>

The orginal setting is not correct, fix it to follow hardware data sheet.
If keep this error setting, mt8173/mt8183 display ok
but mt8192 display abnormal.

Fixes: 0664d139 ("drm/mediatek: Add AAL engine basic function")
Signed-off-by: NYongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>

add description for postmask
postmask is used control round corner for display frame
Signed-off-by: NYongqiang Niu <yongqiang.niu@mediatek.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>

Similar to commit a9d9fea7
("drm/mediatek: mtk_dsi: Create connector for bridges"):

Use the drm_bridge_connector helper to create a connector for pipelines
that use drm_bridge. This allows splitting connector operations across
multiple bridges when necessary, instead of having the last bridge in
the chain creating the connector and handling all connector operations
internally.
Signed-off-by: NHsin-Yi Wang <hsinyi@chromium.org>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>

rdma fifo size may be different even in same SOC, add this
property to the corresponding rdma
Signed-off-by: NYongqiang Niu <yongqiang.niu@mediatek.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>

It's possible that state->base.fb is null. Add a check before access its
format.

Fixes: b6b1bb98 ("drm/mediatek: Turn off Alpha bit when plane format has no alpha")
Signed-off-by: NYongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>