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  1. 31 3月, 2015 2 次提交
  3. 23 12月, 2014 2 次提交
  5. 01 12月, 2014 2 次提交
  7. 28 7月, 2014 3 次提交
  9. 29 5月, 2014 1 次提交
    • H
      mtd: gpmi: add gpmi support for imx6sx · 91f5498e
      由 Huang Shijie 提交于 
      The gpmi's IP for imx6sx is nearly the same as the gpmi's IP for imx6q,
except the following two new features:

     (1) the new BCH contoller has 62-BIT correcting ECC strength
            (The BCH for imx6q only has 40-BIT ECC strength).

     (2) add the hardware Randomizer support.

This patch does the follow changes:

     (1) add a new macro GPMI_IS_MX6SX to represent the imx6sx's gpmi.

     (2) add a new macro GPMI_IS_MX6.
           We use this macro to initialize the same registers for both
         imx6sx and imx6q, and so on.

     (3) add a new gpmi_devdata instance, the gpmi_devdata_imx6sx, for
         imx6sx.
Signed-off-by: NHuang Shijie <b32955@freescale.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
      91f5498e
  11. 16 4月, 2014 1 次提交
    • H
      mtd: gpmi: add gpmi_devdata{} to simplify the code · 6189cccb
      由 Huang Shijie 提交于 
      More and more chips use the GPMI controller, but these chips may use different
version of the IPs for GPMI and BCH. Different IPs have
 different features, such as the BCH's maximum ECC strength:

     imx23/imx28 -- the BCH's maximum ECC strength is 20
     imx6q       -- the BCH's maximum ECC strength is 40
     imx6sx      -- the BCH's maximum ECC strength is 62

This patch does the following things:

  [1] add a new data structure, gpmi_devdata{}, to store the information for
      each IP. Besides the IP version, we store the following information:
         <1> BCH's maximum ECC strength.
         <2> the maximum chain delay in ns used by the EDO mode.

      but we may add more information in future.

  [2] add the gpmi_devdata_imx{23|28|6q} to replace the gpmi_ids.

  [3] simplify the code by using the ECC strength from gpmi_devdata, such as
      gpmi_check_ecc() and legacy_set_geometry();

  [4] use the maximum chain delay to initialize the EDO mode,
      see gpmi_compute_edo_timing().

  [5] rewrite the macros, such GPMI_IS_MX{23|28|6Q}.
Signed-off-by: NHuang Shijie <b32955@freescale.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
      6189cccb
  13. 11 3月, 2014 2 次提交
    • H
      mtd: gpmi: add subpage read support · b8e2931d
      由 Huang Shijie 提交于 
      1) Why add the subpage read support?
  The page size of the nand chip becomes larger and larger, the imx6 has to
  supports the 16K page or even bigger page. But sometimes, the upper layer only
  needs a small part of the page, such as 512 bytes or less.

  For example, ubiattach may only read 64 bytes per page.

2) We only enable the subpage read support when it meets the conditions:
   <1> the chip is imx6 (or later chips) which can supports large nand page.
   <2> the size of ECC parity is byte aligned.
       If the size of ECC parity is not byte aligned, the calling of NAND_CMD_RNDOUT
       will fail.

3) What does this patch do?
   This patch will fake a virtual small page for the subpage read, and call the
   gpmi_ecc_read_page() to do the real work.

   In order to fake a virtual small page, the patch changes the BCH registers and
   the bch_geometry{}. After the subpage read finished, we will restore them back.

4) Performace:
    4.1) Tested with Toshiba TC58NVG2S0F(4096 + 224) with the following command:
         #ubiattach /dev/ubi_ctrl -m 4

       The detail information of /dev/mtd4 shows below:
       --------------------------------------------------------------
       #mtdinfo /dev/mtd4
        mtd4
        Name:                           test
        Type:                           nand
        Eraseblock size:                262144 bytes, 256.0 KiB
        Amount of eraseblocks:          1856 (486539264 bytes, 464.0 MiB)
        Minimum input/output unit size: 4096 bytes
        Sub-page size:                  4096 bytes
        OOB size:                       224 bytes
        Character device major/minor:   90:8
        Bad blocks are allowed:         true
        Device is writable:             true
       --------------------------------------------------------------

    4.2) Before this patch:
       --------------------------------------------------------------
       [   94.530495] UBI: attaching mtd4 to ubi0
       [   98.928850] UBI: scanning is finished
       [   98.953594] UBI: attached mtd4 (name "test", size 464 MiB) to ubi0
       [   98.958562] UBI: PEB size: 262144 bytes (256 KiB), LEB size: 253952 bytes
       [   98.964076] UBI: min./max. I/O unit sizes: 4096/4096, sub-page size 4096
       [   98.969518] UBI: VID header offset: 4096 (aligned 4096), data offset: 8192
       [   98.975128] UBI: good PEBs: 1856, bad PEBs: 0, corrupted PEBs: 0
       [   98.979843] UBI: user volume: 1, internal volumes: 1, max. volumes count: 128
       [   98.985878] UBI: max/mean erase counter: 2/1, WL threshold: 4096, image sequence number: 2024916145
       [   98.993635] UBI: available PEBs: 0, total reserved PEBs: 1856, PEBs reserved for bad PEB handling: 40
       [   99.001807] UBI: background thread "ubi_bgt0d" started, PID 831
       --------------------------------------------------------------
       The attach time is about 98.9 - 94.5 = 4.4s

    4.3) After this patch:
       --------------------------------------------------------------
       [  286.464906] UBI: attaching mtd4 to ubi0
       [  289.186129] UBI: scanning is finished
       [  289.211416] UBI: attached mtd4 (name "test", size 464 MiB) to ubi0
       [  289.216360] UBI: PEB size: 262144 bytes (256 KiB), LEB size: 253952 bytes
       [  289.221858] UBI: min./max. I/O unit sizes: 4096/4096, sub-page size 4096
       [  289.227293] UBI: VID header offset: 4096 (aligned 4096), data offset: 8192
       [  289.232878] UBI: good PEBs: 1856, bad PEBs: 0, corrupted PEBs: 0
       [  289.237628] UBI: user volume: 0, internal volumes: 1, max. volumes count: 128
       [  289.243553] UBI: max/mean erase counter: 1/1, WL threshold: 4096, image sequence number: 2024916145
       [  289.251348] UBI: available PEBs: 1812, total reserved PEBs: 44, PEBs reserved for bad PEB handling: 40
       [  289.259417] UBI: background thread "ubi_bgt0d" started, PID 847
       --------------------------------------------------------------
       The attach time is about 289.18 - 286.46 = 2.7s

     4.4) The conclusion:
       We achieve (4.4 - 2.7) / 4.4 = 38.6% faster in the ubiattach.
Signed-off-by: NHuang Shijie <b32955@freescale.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
      b8e2931d
    • H
      mtd: gpmi: do not use the mtd->writesize · 4a57d670
      由 Huang Shijie 提交于 
      The nfc_geo->payload_size is equal to the mtd->writesize now,
use the nfc_geo->payload_size to replace the mtd->writesize.

This patch makes preparation for the gpmi's subpage read support.
In the subpage support, the nfc_geo->payload_size maybe smaller then
the mtd->writesize.
Signed-off-by: NHuang Shijie <b32955@freescale.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
      4a57d670
  15. 28 1月, 2014 2 次提交
    • H
      mtd: gpmi: add sanity check when mapping DMA for read_buf/write_buf · 0ff76a92
      由 Huang Shijie 提交于 
      The buffer pointer passed from the upper layer may points to
a buffer in the stack or a buffer allocated by vmalloc, and etc..

This patch adds more sanity check to this buffer.
After this patch, if we meet a buffer which is allocated by vmalloc or
a buffer in the stack, we will use our own DMA buffer @data_buffer_dma
to do the DMA operations. If the buffer is not the cases above, we will
map it for DMA operations directly.
Signed-off-by: NHuang Shijie <shijie8@gmail.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
      0ff76a92
    • H
      mtd: gpmi: allocate a proper buffer for non ECC read/write · 06f216c8
      由 Huang Shijie 提交于 
      The @data_buffer_dma buffer is used for non ECC read/write.

Currently, the length of the buffer is PAGE_SIZE, but the NAND chip may
has 8K page or 16K page. So we have to extend it for the large page NAND
chips.

The gpmi_alloc_dma_buffer will be called twice. The first time is to
allocate a temporary buffer for scanning the NAND chip; The second time
is to allocate a buffer to store the real page content.

This patch allocates a buffer of PAGE_SIZE size for scanning the NAND
chip when gpmi_alloc_dma_buffer is called the first time, and allocates a
buffer of the real NAND page size for the second time gpmi_alloc_dma_buffer
is called.
Signed-off-by: NHuang Shijie <shijie8@gmail.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
      06f216c8
  17. 04 1月, 2014 9 次提交
  19. 13 11月, 2013 1 次提交
    • H
      mtd: gpmi: fix the NULL pointer · 885d71e5
      由 Huang Shijie 提交于 
      The imx23 board will check the fingerprint, so it will call the
mx23_check_transcription_stamp. This function will use @chip->buffers->databuf
as its buffer which is allocated in the nand_scan_tail().

Unfortunately, the mx23_check_transcription_stamp is called before the
nand_scan_tail(). So we will meet a NULL pointer bug:

--------------------------------------------------------------------
[    1.150000] NAND device: Manufacturer ID: 0xec, Chip ID: 0xd7 (Samsung NAND 4GiB 3,3V 8-bit), 4096MiB, page size: 4096, OOB size: 8
[    1.160000] Unable to handle kernel NULL pointer dereference at virtual address 000005d0
[    1.170000] pgd = c0004000
[    1.170000] [000005d0] *pgd=00000000
[    1.180000] Internal error: Oops: 5 [#1] ARM
[    1.180000] Modules linked in:
[    1.180000] CPU: 0 PID: 1 Comm: swapper Not tainted 3.12.0 #89
[    1.180000] task: c7440000 ti: c743a000 task.ti: c743a000
[    1.180000] PC is at memcmp+0x10/0x54
[    1.180000] LR is at gpmi_nand_probe+0x42c/0x894
[    1.180000] pc : [<c025fcb0>]    lr : [<c02f6a68>]    psr: 20000053
[    1.180000] sp : c743be2c  ip : 600000d3  fp : ffffffff
[    1.180000] r10: 000005d0  r9 : c02f5f08  r8 : 00000000
[    1.180000] r7 : c75858a8  r6 : c75858a8  r5 : c7585b18  r4 : c7585800
[    1.180000] r3 : 000005d0  r2 : 00000004  r1 : c05c33e4  r0 : 000005d0
[    1.180000] Flags: nzCv  IRQs on  FIQs off  Mode SVC_32  ISA ARM  Segment kernel
[    1.180000] Control: 0005317f  Table: 40004000  DAC: 00000017
[    1.180000] Process swapper (pid: 1, stack limit = 0xc743a1c0)
--------------------------------------------------------------------

This patch rearrange the init procedure:
   Set the NAND_SKIP_BBTSCAN to skip the nand scan firstly, and after we
   set the proper settings, we will call the chip->scan_bbt() manually.

Cc: stable@vger.kernel.org # 3.12
Signed-off-by: NHuang Shijie <b32955@freescale.com>
Reported-by: NFabio Estevam <festevam@gmail.com>
Tested-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
      885d71e5
  21. 12 11月, 2013 2 次提交
    • H
      mtd: gpmi: fix kernel BUG due to racing DMA operations · 7b3d2fb9
      由 Huang Shijie 提交于 
      [1] The gpmi uses the nand_command_lp to issue the commands to NAND chips.
    The gpmi issues a DMA operation with gpmi_cmd_ctrl when it handles
    a NAND_CMD_NONE control command. So when we read a page(NAND_CMD_READ0)
    from the NAND, we may send two DMA operations back-to-back.

    If we do not serialize the two DMA operations, we will meet a bug when

    1.1) we enable CONFIG_DMA_API_DEBUG, CONFIG_DMADEVICES_DEBUG,
         and CONFIG_DEBUG_SG.

    1.2) Use the following commands in an UART console and a SSH console:
         cmd 1: while true;do dd if=/dev/mtd0 of=/dev/null;done
         cmd 1: while true;do dd if=/dev/mmcblk0 of=/dev/null;done

    The kernel log shows below:
    -----------------------------------------------------------------
    kernel BUG at lib/scatterlist.c:28!
    Unable to handle kernel NULL pointer dereference at virtual address 00000000
      .........................
    [<80044a0c>] (__bug+0x18/0x24) from [<80249b74>] (sg_next+0x48/0x4c)
    [<80249b74>] (sg_next+0x48/0x4c) from [<80255398>] (debug_dma_unmap_sg+0x170/0x1a4)
    [<80255398>] (debug_dma_unmap_sg+0x170/0x1a4) from [<8004af58>] (dma_unmap_sg+0x14/0x6c)
    [<8004af58>] (dma_unmap_sg+0x14/0x6c) from [<8027e594>] (mxs_dma_tasklet+0x18/0x1c)
    [<8027e594>] (mxs_dma_tasklet+0x18/0x1c) from [<8007d444>] (tasklet_action+0x114/0x164)
    -----------------------------------------------------------------

    1.3) Assume the two DMA operations is X (first) and Y (second).

         The root cause of the bug:
	   Assume process P issues DMA X, and sleep on the completion
	 @this->dma_done. X's tasklet callback is dma_irq_callback. It firstly
	 wake up the process sleeping on the completion @this->dma_done,
	 and then trid to unmap the scatterlist S. The waked process P will
	 issue Y in another ARM core. Y initializes S->sg_magic to zero
	 with sg_init_one(), while dma_irq_callback is unmapping S at the same
	 time.

	 See the diagram:

                   ARM core 0              |         ARM core 1
	 -------------------------------------------------------------
         (P issues DMA X, then sleep)  --> |
                                           |
         (X's tasklet wakes P)         --> |
                                           |
                                           | <-- (P begin to issue DMA Y)
                                           |
         (X's tasklet unmap the            |
      scatterlist S with dma_unmap_sg) --> | <-- (Y calls sg_init_one() to init
                                           |      scatterlist S)
                                           |

[2] This patch serialize both the X and Y in the following way:
     Unmap the DMA scatterlist S firstly, and wake up the process at the end
     of the DMA callback, in such a way, Y will be executed after X.

     After this patch:

                   ARM core 0              |         ARM core 1
	 -------------------------------------------------------------
         (P issues DMA X, then sleep)  --> |
                                           |
         (X's tasklet unmap the            |
      scatterlist S with dma_unmap_sg) --> |
                                           |
         (X's tasklet wakes P)         --> |
                                           |
                                           | <-- (P begin to issue DMA Y)
                                           |
                                           | <-- (Y calls sg_init_one() to init
                                           |     scatterlist S)
                                           |

Cc: stable@vger.kernel.org # 3.2
Signed-off-by: NHuang Shijie <b32955@freescale.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
      7b3d2fb9
    • H
      mtd: gpmi: only scan two chips for imx6 · 80bd33ac
      由 Huang Shijie 提交于 
      We cannot scan two chips for imx23 and imx28:
  imx23: the Ready-Busy1 line is not connected for some board.
  imx28: we do not set the pinctrl for Ready-Busy1

So we only scan two chips for imx6.
Signed-off-by: NHuang Shijie <b32955@freescale.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
      80bd33ac
  23. 08 11月, 2013 1 次提交
  25. 07 11月, 2013 2 次提交
  27. 28 10月, 2013 2 次提交
  29. 26 10月, 2013 1 次提交
    • D
      mtd: gpmi: fix ECC regression · 031e2777
      由 David Woodhouse 提交于 
      The "legacy" ECC layout used until 3.12-rc1 uses all the OOB area by
computing the ECC strength and ECC step size ourselves.

Commit 2febcdf8 ("mtd: gpmi: set the BCHs geometry with the ecc info")
makes the driver use the ECC info (ECC strength and ECC step size)
provided by the MTD code, and creates a different NAND ECC layout
for the BCH, and use the new ECC layout. This causes a regression:

   We can not mount the ubifs which was created by the old NAND ECC layout.

This patch fixes this issue by reverting to the legacy ECC layout.

We will probably introduce a new device-tree property to indicate that
the new ECC layout can be used. For now though, for the imminent 3.12
release, we just unconditionally revert to the 3.11 behaviour.

This leaves a harmless cosmetic warning about an unused function. At
this point in the cycle I really don't care.
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Acked-by: NHuang Shijie <b32955@freescale.com>
Acked-by: NMarek Vasut <marex@denx.de>
Tested-by: NMarek Vasut <marex@denx.de>
      031e2777
  31. 31 8月, 2013 3 次提交
  33. 30 8月, 2013 1 次提交
    • B
      mtd: nand: refactor chip->block_markbad interface · 5a0edb25
      由 Brian Norris 提交于 
      The chip->block_markbad pointer should really only be responsible for
writing a bad block marker for new bad blocks. It should not take care
of BBT-related functionality, nor should it handle bookkeeping of bad
block stats.

This patch refactors the 3 users of the block_markbad interface (plus
the default nand_base implementation) so that the common code is kept in
nand_block_markbad_lowlevel(). It removes some inconsistencies between
the various implementations and should allow for more centralized
improvements in the future.

Because gpmi-nand no longer needs the nand_update_bbt() function, let's
stop exporting it as well.
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Acked-by: Huang Shijie <b32955@freescale.com> (for gpmi-nand parts)
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
      5a0edb25
  35. 06 8月, 2013 3 次提交