1. 19 9月, 2017 2 次提交
  2. 29 8月, 2017 1 次提交
  3. 30 7月, 2017 1 次提交
  4. 18 7月, 2017 1 次提交
  5. 17 7月, 2017 1 次提交
  6. 29 6月, 2017 6 次提交
    • D
      tty: serial: lpuart: add a more accurate baud rate calculation method · a6d7514b
      Dong Aisheng 提交于
      On new LPUART versions, the oversampling ratio for the receiver can be
      changed from 4x (00011) to 32x (11111) which could help us get a more
      accurate baud rate divider.
      
      The idea is to use the best OSR (over-sampling rate) possible.
      Note, OSR is typically hard-set to 16 in other LPUART instantiations.
      Loop to find the best OSR value possible, one that generates minimum
      baud diff iterate through the rest of the supported values of OSR.
      
      Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      Cc: Jiri Slaby <jslaby@suse.com>
      Cc: Stefan Agner <stefan@agner.ch>
      Cc: Mingkai Hu <Mingkai.Hu@nxp.com>
      Cc: Yangbo Lu <yangbo.lu@nxp.com>
      Acked-by: NFugang Duan <fugang.duan@nxp.com>
      Signed-off-by: NDong Aisheng <aisheng.dong@nxp.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      a6d7514b
    • D
      tty: serial: lpuart: add earlycon support for imx7ulp · 97d6f353
      Dong Aisheng 提交于
      earlycon is executed quite early before the device tree probe,
      so we need correctly initialize the port membase and iotype for
      imx7ulp during early console setup before using.
      
      Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      Cc: Jiri Slaby <jslaby@suse.com>
      Cc: Stefan Agner <stefan@agner.ch>
      Cc: Mingkai Hu <Mingkai.Hu@nxp.com>
      Cc: Yangbo Lu <yangbo.lu@nxp.com>
      Acked-by: NFugang Duan <fugang.duan@nxp.com>
      Signed-off-by: NDong Aisheng <aisheng.dong@nxp.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      97d6f353
    • D
      tty: serial: lpuart: add imx7ulp support · 24b1e5f0
      Dong Aisheng 提交于
      The lpuart of imx7ulp is basically the same as ls1021a. It's also
      32 bit width register, but unlike ls1021a, it's little endian.
      Besides that, imx7ulp lpuart has a minor different register layout
      from ls1021a that it has four extra registers (verid, param, global,
      pincfg) located at the beginning of register map, which are currently
      not used by the driver and less to be used later.
      
      To ease the register difference handling, we add a reg_off member
      in lpuart_soc_data structure to represent if the normal
      lpuart32_{read|write} requires plus a offset to hide the issue.
      
      Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      Cc: Jiri Slaby <jslaby@suse.com>
      Cc: Stefan Agner <stefan@agner.ch>
      Cc: Mingkai Hu <Mingkai.Hu@nxp.com>
      Cc: Yangbo Lu <yangbo.lu@nxp.com>
      Cc: Fugang Duan <fugang.duan@nxp.com>
      Signed-off-by: NDong Aisheng <aisheng.dong@nxp.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      24b1e5f0
    • D
      tty: serial: lpuart: add little endian 32 bit register support · f98e1fcd
      Dong Aisheng 提交于
      Use standard port->iotype to distinguish endian difference. Note as we
      read/write register by checking iotype dynamically, we need to initialize
      the iotype correctly for earlycon as well to avoid a break.
      
      Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      Cc: Jiri Slaby <jslaby@suse.com> (supporter:TTY LAYER)
      Cc: Stefan Agner <stefan@agner.ch>
      Cc: Mingkai Hu <Mingkai.Hu@nxp.com>
      Cc: Yangbo Lu <yangbo.lu@nxp.com>
      Cc: Fugang Duan <fugang.duan@nxp.com>
      Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
      Cc: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
      Signed-off-by: NDong Aisheng <aisheng.dong@nxp.com>
      
      ChangeLog:
      v3->v4:
       * Removed unneeded semicolon catched by 0day Robot.
      v2->v3:
       * Instead of using global var, use standard port->iotype to distinguish
         endian difference.
      v1->v2:
       * No changes
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      f98e1fcd
    • D
      tty: serial: lpuart: refactor lpuart32_{read|write} prototype · a0204f25
      Dong Aisheng 提交于
      Due to the original lpuart32_read/write takes no port specific
      information arguments, it's hard to distinguish port difference
      within the API. Although it works before, but not suitable anymore
      when adding more new chips support.
      
      So let's convert it to accept a new struct uart_port argument
      to make it be able to retrieve more port specific information.
      This is a preparation for the later adding new chips support
      more easily. No functions changes.
      
      Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      Cc: Jiri Slaby <jslaby@suse.com>
      Cc: Stefan Agner <stefan@agner.ch>
      Cc: Mingkai Hu <Mingkai.Hu@nxp.com>
      Cc: Yangbo Lu <yangbo.lu@nxp.com>
      Cc: Fugang Duan <fugang.duan@nxp.com>
      Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
      Cc: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
      Signed-off-by: NDong Aisheng <aisheng.dong@nxp.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      a0204f25
    • D
      tty: serial: lpuart: introduce lpuart_soc_data to represent SoC property · 0d6fce90
      Dong Aisheng 提交于
      This is used to dynamically check the SoC specific lpuart properies.
      Currently only the iotype is added, it functions the same as before.
      With this, new chips with different iotype will be more easily added.
      
      Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      Cc: Jiri Slaby <jslaby@suse.com>
      Cc: Stefan Agner <stefan@agner.ch>
      Cc: Mingkai Hu <Mingkai.Hu@nxp.com>
      Cc: Yangbo Lu <yangbo.lu@nxp.com>
      Cc: Fugang Duan <fugang.duan@nxp.com>
      Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
      Cc: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
      Signed-off-by: NDong Aisheng <aisheng.dong@nxp.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      0d6fce90
  7. 31 3月, 2017 1 次提交
  8. 12 1月, 2017 1 次提交
  9. 28 10月, 2016 1 次提交
  10. 27 10月, 2016 2 次提交
  11. 15 9月, 2016 1 次提交
  12. 02 9月, 2016 1 次提交
    • J
      tty: serial: constify uart_ops structures · 069a47e5
      Julia Lawall 提交于
      Check for uart_ops structures that are only stored in the ops field of a
      uart_port structure.  This field is declared const, so uart_ops structures
      that have this property can be declared as const also.
      
      The semantic patch that makes this change is as follows:
      (http://coccinelle.lip6.fr/)
      
      // <smpl>
      @r disable optional_qualifier@
      identifier i;
      position p;
      @@
      static struct uart_ops i@p = { ... };
      
      @ok@
      identifier r.i;
      struct uart_port e;
      position p;
      @@
      e.ops = &i@p;
      
      @bad@
      position p != {r.p,ok.p};
      identifier r.i;
      struct uart_ops e;
      @@
      e@i@p
      
      @depends on !bad disable optional_qualifier@
      identifier r.i;
      @@
      static
      +const
       struct uart_ops i = { ... };
      // </smpl>
      Signed-off-by: NJulia Lawall <Julia.Lawall@lip6.fr>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      069a47e5
  13. 31 8月, 2016 8 次提交
  14. 26 6月, 2016 1 次提交
    • J
      TTY: serial, handle platform_get_irq retval properly · 394a9e2c
      Jiri Slaby 提交于
      platform_get_irq can fail, so we should handle negative value when
      returned.
      
      [v2]
      
      platform_get_irq can actually return zero on some platforms. So do not
      remove checks for irq == 0 there.
      Signed-off-by: NJiri Slaby <jslaby@suse.cz>
      Cc: Russell King <linux@arm.linux.org.uk>
      Cc: "Uwe Kleine-König" <kernel@pengutronix.de>
      Cc: Russell King <linux@armlinux.org.uk>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Michael Ellerman <mpe@ellerman.id.au>
      Cc: Laxman Dewangan <ldewangan@nvidia.com>
      Cc: Stephen Warren <swarren@wwwdotorg.org>
      Cc: Thierry Reding <thierry.reding@gmail.com>
      Cc: Alexandre Courbot <gnurou@gmail.com>
      Cc: linux-serial@vger.kernel.org
      Cc: linux-kernel@vger.kernel.org
      Cc: linuxppc-dev@lists.ozlabs.org
      Cc: linux-tegra@vger.kernel.org
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      394a9e2c
  15. 18 10月, 2015 1 次提交
  16. 27 3月, 2015 3 次提交
  17. 03 2月, 2015 6 次提交
    • S
      tty: serial: fsl_lpuart: terminate DMA on buffer flush · bfc2e07f
      Stefan Agner 提交于
      On uart buffer flush, serial core resets the circular buffer.
      If a DMA transfer is in progress at that time, the callback
      lpuart_dma_tx_complete will move buffer's tail unconditionally,
      hence tail moves beyond head. Use the flush_buffer hook to
      terminate the DMA imeaditely and avoid lpuart_dma_tx_complete
      being called in this situation.
      
      This bug often showed up while shutdown and lead to duplicate
      serial console output.
      Signed-off-by: NStefan Agner <stefan@agner.ch>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      bfc2e07f
    • Y
      serial: fsl-lpuart: disable interrupt when suspend · 2fe605df
      Yuan Yao 提交于
      For power management support, we should disable TX and
      TX interrupt so that kernel can prepare for deep sleep.
      
      Retain RX and RX interrupt for wakeup the kernel when
      receive the input character.
      Signed-off-by: NYuan Yao <yao.yuan@freescale.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      2fe605df
    • S
      serial: fsl_lpuart: update RX timer on successful DMA transfer · 011f5bde
      Stefan Agner 提交于
      To end a DMA transfer which did not consume a whole buffer (e.g. one
      character only), a RX timer is used. When lots of data are received
      the DMA transfer will complete and setup another DMA transfer, which
      in turn might complete again. In this cases, it is not necessary to
      abort the DMA transfers using the RX timer. This change pushes the
      RX timer timeout into the future each time a DMA transfer completed.
      
      Aborting the DMA was not very harmful, since the next received
      character lead to setup of another RX DMA.
      Signed-off-by: NStefan Agner <stefan@agner.ch>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      011f5bde
    • S
      serial: fsl_lpuart: move DMA channel request to probe · 4a818c43
      Stefan Agner 提交于
      Move the DMA channel request to probe to avoid requesting the DMA
      channel on each opening of the ttyLPx device. This also fixes a
      potential issue that TX channel is not freed when only RX channel
      allocation fails. The DMA channels are now handled independently,
      so one could use UART with DMA only in TX direction for instance.
      Signed-off-by: NStefan Agner <stefan@agner.ch>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      4a818c43
    • S
      serial: fsl_lpuart: avoid new transfer while DMA is running · 5f1437f6
      Stefan Agner 提交于
      When the UART is in DMA receive mode (RDMAS set) and one character
      just arrived while another interrupt is handled (e.g. TX), the RDRF
      (receiver data register full flag) is set due to the water level of
      1. But since the DMA will take care of this character, there is no
      need to handle it by calling lpuart_prepare_rx. Handling it leads to
      adding the RX timeout timer twice:
      
      [   74.336698] Kernel BUG at 80053070 [verbose debug info unavailable]
      [   74.342999] Internal error: Oops - BUG: 0 [#1] ARM0:00.00 khungtaskd
      [   74.347817] Modules linked in:    0 S  0.0  0.0   0:00.00 writeback
      [   74.350926] CPU: 0 PID: 0 Comm: swapper Not tainted 3.19.0-rc3-00001-g39d78e2 #1788
      [   74.358617] Hardware name: Freescale Vybrid VF610 (Device Tree)t
      [   74.364563] task: 807a7678 ti: 8079c000 task.ti: 8079c000 kblockd
      [   74.370002] PC is at add_timer+0x24/0x28.0  0.0   0:00.09 kworker/u2:1
      [   74.373960] LR is at lpuart_int+0x15c/0x3d8
      [   74.378171] pc : [<80053070>]    lr : [<802e0d88>]    psr: a0010193
      [   74.378171] sp : 8079de10  ip : 8079de20  fp : 8079de1c
      [   74.389694] r10: 807d44c0  r9 : 8688c300  r8 : 00000013
      [   74.394943] r7 : 20010193  r6 : 00000000  r5 : 000000a0  r4 : 86997210
      [   74.401498] r3 : ffffa7da  r2 : 80817868  r1 : 86997210  r0 : 86997344
      [   74.408052] Flags: NzCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
      [   74.415489] Control: 10c5387d  Table: 8611c059  DAC: 00000015
      [   74.421265] Process swapper (pid: 0, stack limit = 0x8079c230)
      ...
      
      Solve this by only execute the receiver path (lpuart_prepare_rx) if
      the DMA receive mode (RDMAS) is not set. Also, make sure the flag is
      cleared on initialization, in case it has been left set.
      
      This can be best reproduced using UART as a serial console, then
      running top while dd'ing data into the terminal.
      Signed-off-by: NStefan Agner <stefan@agner.ch>
      Cc: stable <stable@vger.kernel.org> # 3.14
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      5f1437f6
    • S
      serial: fsl_lpuart: delete timer on shutdown · 4a8588a1
      Stefan Agner 提交于
      If the serial port gets closed while a RX transfer is in progress,
      the timer might fire after the serial port shutdown finished. This
      leads in a NULL pointer dereference:
      
      [    7.508324] Unable to handle kernel NULL pointer dereference at virtual address 00000000
      [    7.516590] pgd = 86348000
      [    7.519445] [00000000] *pgd=86179831, *pte=00000000, *ppte=00000000
      [    7.526145] Internal error: Oops: 17 [#1] ARM
      [    7.530611] Modules linked in:
      [    7.533876] CPU: 0 PID: 123 Comm: systemd Not tainted 3.19.0-rc3-00004-g5b11ea7 #1778
      [    7.541827] Hardware name: Freescale Vybrid VF610 (Device Tree)
      [    7.547862] task: 861c3400 ti: 86ac8000 task.ti: 86ac8000
      [    7.553392] PC is at lpuart_timer_func+0x24/0xf8
      [    7.558127] LR is at lpuart_timer_func+0x20/0xf8
      [    7.562857] pc : [<802df99c>]    lr : [<802df998>]    psr: 600b0113
      [    7.562857] sp : 86ac9b90  ip : 86ac9b90  fp : 86ac9bbc
      [    7.574467] r10: 80817180  r9 : 80817b98  r8 : 80817998
      [    7.579803] r7 : 807acee0  r6 : 86989000  r5 : 00000100  r4 : 86997210
      [    7.586444] r3 : 86ac8000  r2 : 86ac9bc0  r1 : 86997210  r0 : 00000000
      [    7.593085] Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
      [    7.600341] Control: 10c5387d  Table: 86348059  DAC: 00000015
      [    7.606203] Process systemd (pid: 123, stack limit = 0x86ac8230)
      
      Setup the timer on UART startup which allows to delete the timer
      unconditionally on shutdown. This also saves the initialization
      on each transfer.
      Signed-off-by: NStefan Agner <stefan@agner.ch>
      Cc: stable <stable@vger.kernel.org> # 3.14
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      4a8588a1
  18. 08 11月, 2014 2 次提交