1. 07 1月, 2020 6 次提交
  2. 06 1月, 2020 1 次提交
  3. 13 12月, 2019 1 次提交
  4. 12 12月, 2019 1 次提交
  5. 22 11月, 2019 1 次提交
  6. 14 11月, 2019 1 次提交
  7. 13 11月, 2019 1 次提交
  8. 12 11月, 2019 6 次提交
  9. 08 11月, 2019 1 次提交
  10. 07 11月, 2019 1 次提交
    • A
      gpiolib: No need to call gpiochip_remove_pin_ranges() twice · 2f4133bb
      Andy Shevchenko 提交于
      of_gpiochip_add(), when fails, calls gpiochip_remove_pin_ranges().
      
      ADD:
        gpiochip_add_data_with_key() ->
          of_gpiochip_add() -> (ERROR path)
            gpiochip_remove_pin_ranges()
      
      At the same time of_gpiochip_remove() calls exactly the above mentioned
      function unconditionally and so does gpiochip_remove().
      
      REMOVE:
        gpiochip_remove() ->
          gpiochip_remove_pin_ranges()
          of_gpiochip_remove() ->
            gpiochip_remove_pin_ranges()
      
      Since gpiochip_remove() calls gpiochip_remove_pin_ranges() unconditionally,
      we have duplicate call to the same function when it's not necessary.
      
      Move gpiochip_remove_pin_ranges() from of_gpiochip_add() to gpiochip_add()
      to avoid duplicate calls and be consistent with the explicit call in
      gpiochip_remove().
      
      Fixes: e93fa3f2 ("gpiolib: remove duplicate pin range code")
      Depends-on: f7299d44 ("gpio: of: Fix of_gpiochip_add() error path")
      Cc: Geert Uytterhoeven <geert+renesas@glider.be>
      Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      2f4133bb
  11. 05 11月, 2019 1 次提交
  12. 15 10月, 2019 1 次提交
  13. 06 10月, 2019 1 次提交
  14. 03 10月, 2019 1 次提交
  15. 01 10月, 2019 2 次提交
  16. 12 9月, 2019 1 次提交
  17. 11 9月, 2019 1 次提交
  18. 09 9月, 2019 2 次提交
  19. 06 9月, 2019 1 次提交
  20. 04 9月, 2019 1 次提交
  21. 23 8月, 2019 2 次提交
  22. 20 8月, 2019 2 次提交
  23. 15 8月, 2019 1 次提交
    • L
      gpio: Add support for hierarchical IRQ domains · fdd61a01
      Linus Walleij 提交于
      Hierarchical IRQ domains can be used to stack different IRQ
      controllers on top of each other.
      
      Bring hierarchical IRQ domains into the GPIOLIB core with the
      following basic idea:
      
      Drivers that need their interrupts handled hierarchically
      specify a callback to translate the child hardware IRQ and
      IRQ type for each GPIO offset to a parent hardware IRQ and
      parent hardware IRQ type.
      
      Users have to pass the callback, fwnode, and parent irqdomain
      before calling gpiochip_irqchip_add().
      
      We use the new method of just filling in the struct
      gpio_irq_chip before adding the gpiochip for all hierarchical
      irqchips of this type.
      
      The code path for device tree is pretty straight-forward,
      while the code path for old boardfiles or anything else will
      be more convoluted requireing upfront allocation of the
      interrupts when adding the chip.
      
      One specific use-case where this can be useful is if a power
      management controller has top-level controls for wakeup
      interrupts. In such cases, the power management controller can
      be a parent to other interrupt controllers and program
      additional registers when an IRQ has its wake capability
      enabled or disabled.
      
      The hierarchical irqchip helper code will only be available
      when IRQ_DOMAIN_HIERARCHY is selected to GPIO chips using
      this should select or depend on that symbol. When using
      hierarchical IRQs, the parent interrupt controller must
      also be hierarchical all the way up to the top interrupt
      controller wireing directly into the CPU, so on systems
      that do not have this we can get rid of all the extra
      code for supporting hierarchical irqs.
      
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Lina Iyer <ilina@codeaurora.org>
      Cc: Jon Hunter <jonathanh@nvidia.com>
      Cc: Sowjanya Komatineni <skomatineni@nvidia.com>
      Cc: Bitan Biswas <bbiswas@nvidia.com>
      Cc: linux-tegra@vger.kernel.org
      Cc: David Daney <david.daney@cavium.com>
      Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
      Cc: Brian Masney <masneyb@onstation.org>
      Signed-off-by: NThierry Reding <treding@nvidia.com>
      Signed-off-by: NBrian Masney <masneyb@onstation.org>
      Co-developed-by: NBrian Masney <masneyb@onstation.org>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      Link: https://lore.kernel.org/r/20190808123242.5359-1-linus.walleij@linaro.org
      fdd61a01
  24. 14 8月, 2019 1 次提交
  25. 03 8月, 2019 1 次提交
  26. 01 8月, 2019 1 次提交