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  1. 18 2月, 2016 2 次提交
  3. 03 12月, 2015 1 次提交
  5. 02 12月, 2015 1 次提交
    • A
      i40e/i40evf: Fix RS bit update in Tx path and disable force WB workaround · 6a7fded7
      由 Anjali Singhai Jain 提交于 
      This patch fixes the issue of forcing WB too often causing us to not
benefit from NAPI.

Without this patch we were forcing WB/arming interrupt too often taking
away the benefits of NAPI and causing a performance impact.

With this patch we disable force WB in the clean routine for X710
and XL710 adapters. X722 adapters do not enable interrupt to force
a WB and benefit from WB_ON_ITR and hence force WB is left enabled
for those adapters.
For XL710 and X710 adapters if we have less than 4 packets pending
a software Interrupt triggered from service task will force a WB.

This patch also changes the conditions for setting RS bit as described
in code comments. This optimizes when the HW does a tail bump amd when
it does a WB. It also optimizes when we do a wmb.

Change-ID: Id831e1ae7d3e2ec3f52cd0917b41ce1d22d75d9d
Signed-off-by: NAnjali Singhai Jain <anjali.singhai@intel.com>
Tested-by: NAndrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
      6a7fded7
  7. 26 11月, 2015 1 次提交
  9. 20 10月, 2015 3 次提交
  11. 16 10月, 2015 1 次提交
    • J
      i40e/i40evf: moderate interrupts differently · ac26fc13
      由 Jesse Brandeburg 提交于 
      The XL710 hardware has a different interrupt moderation design
that can support a limit of total interrupts per second per
vector, in addition to the "number of interrupts per second"
controls already established in the driver.  This combination
of hardware features allows us to set very low default latency
settings but minimize the total CPU utilization by not
making too many interrupts, should the user desire.

The current driver implementation is still enabling the dynamic
moderation in the driver, and only using the rx/tx-usecs
limit in ethtool to limit the interrupt rate per second, by default.

The new code implemented in this patch
2) adds init/use of the new "Interrupt Limit" register
3) adds ethtool knob to control/report the limits above

Usage is ethtool -C ethx rx-usecs-high <value> Where <value> is number
of microseconds to create a rate of 1/N interrupts per second,
regardless of rx-usecs or tx-usecs values. Since there is a credit based
scheme in the hardware, the rx-usecs and tx-usecs can be configured for
very low latency for short bursts, but once the credit runs out the
refill rate on the credits is limited by rx-usecs-high.

Change-ID: I3a1075d3296123b0f4f50623c779b027af5b188d
Signed-off-by: NJesse Brandeburg <jesse.brandeburg@intel.com>
Tested-by: NAndrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
      ac26fc13
  13. 09 10月, 2015 1 次提交
  15. 08 10月, 2015 1 次提交
  17. 29 9月, 2015 1 次提交
  19. 06 8月, 2015 3 次提交
  21. 23 7月, 2015 1 次提交
  23. 28 5月, 2015 2 次提交
  25. 26 2月, 2015 1 次提交
  27. 24 2月, 2015 1 次提交
    • M
      i40e/i40evf: Refactor the receive routines · a132af24
      由 Mitch Williams 提交于 
      Split the receive hot path code into two, one for packet split and one
for single buffer. This improves receive performance since we only need
to check if the ring is in packet split mode once per NAPI poll time,
not several times per packet. The single buffer code is further improved
by the removal of a bunch of code and several variables that are not
needed. On a receive-oriented test this can improve single-threaded
throughput.

Also refactor the packet split receive path to use a fixed buffer for
headers, like ixgbe does. This vastly reduces the number of DMA mappings
and unmappings we need to do, allowing for much better performance in
the presence of an IOMMU.

Lastly, correct packet split descriptor types now that we are actually
using them.

Change-ID: I3a194a93af3d2c31e77ff17644ac7376da6f3e4b
Signed-off-by: NMitch Williams <mitch.a.williams@intel.com>
Tested-by: NJim Young <james.m.young@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
      a132af24
  29. 09 2月, 2015 1 次提交
  31. 11 11月, 2014 1 次提交
  33. 27 8月, 2014 1 次提交
  35. 03 7月, 2014 1 次提交
  37. 25 6月, 2014 1 次提交
  39. 08 6月, 2014 1 次提交
    • J
      i40e/i40evf: fix TSO accounting · 980093eb
      由 Jesse Brandeburg 提交于 
      The TSO logic in the transmit path had some assumptions that
have been broken now that the kernel can send as much as 32kB
in a single skb->frag[.] entry, even on a system with 4kB pages.

This fixes the assumptions and allows the kernel to operate
as efficiently as possible with both SENDFILE and SEND.

In addition, the hardware limit of data contained in a descriptor is
changed to the next power of two below where it currently is in
order to align to a power of two value, preventing a single byte
of data in a descriptor.

Change-ID: I6af1f0b87c1458e10644dbd47541591075a52651
Signed-off-by: NJesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
      980093eb
  41. 05 6月, 2014 1 次提交
  43. 29 5月, 2014 2 次提交
  45. 21 5月, 2014 1 次提交
  47. 01 1月, 2014 1 次提交
  49. 10 12月, 2013 1 次提交
  51. 10 10月, 2013 8 次提交