1. 24 5月, 2019 1 次提交
  2. 07 12月, 2018 2 次提交
  3. 03 10月, 2018 15 次提交
  4. 31 7月, 2018 1 次提交
  5. 20 7月, 2018 1 次提交
  6. 18 7月, 2018 2 次提交
  7. 02 5月, 2018 1 次提交
  8. 27 4月, 2018 1 次提交
    • S
      mtd: rawnand: davinci: don't acquire and enable clock · a8e3923a
      Sekhar Nori 提交于
      NAND itself is an asynchronous interface, it does not have any
      clock input. DaVinci NAND driver acquires clock for AEMIF
      (asynchronous external memory interface) which is an on-chip
      IP to which NAND is connected.
      
      The same clock is also enabled in AEMIF driver (either present
      drivers/memory or from machine code for some older platforms).
      AEMIF timing must be initialized before NAND can be accessed.
      This ensures that AEMIF clock is enabled too.
      
      Remove the superfluous clock acquisition and enable in DaVinci
      NAND driver.
      
      Tested on K2L, K2HK, K2E, DA850 EVM, DA850 LCDK in device-tree
      boot and DM644x EVM in legacy boot.
      Signed-off-by: NSekhar Nori <nsekhar@ti.com>
      Tested-by: NBartosz Golaszewski <bgolaszewski@baylibre.com>
      Signed-off-by: NBoris Brezillon <boris.brezillon@bootlin.com>
      a8e3923a
  9. 29 3月, 2018 1 次提交
  10. 16 2月, 2018 1 次提交
  11. 13 8月, 2017 1 次提交
  12. 15 5月, 2017 1 次提交
  13. 25 4月, 2017 1 次提交
  14. 10 9月, 2016 1 次提交
    • K
      mtd: nand: davinci: Reinitialize the HW ECC engine in 4bit hwctl · f6d7c1b5
      Karl Beldan 提交于
      This fixes subpage writes when using 4-bit HW ECC.
      
      There has been numerous reports about ECC errors with devices using this
      driver for a while.  Also the 4-bit ECC has been reported as broken with
      subpages in [1] and with 16 bits NANDs in the driver and in mach* board
      files both in mainline and in the vendor BSPs.
      
      What I saw with 4-bit ECC on a 16bits NAND (on an LCDK) which got me to
      try reinitializing the ECC engine:
      - R/W on whole pages properly generates/checks RS code
      - try writing the 1st subpage only of a blank page, the subpage is well
        written and the RS code properly generated, re-reading the same page
        the HW detects some ECC error, reading the same page again no ECC
        error is detected
      
      Note that the ECC engine is already reinitialized in the 1-bit case.
      
      Tested on my LCDK with UBI+UBIFS using subpages.
      This could potentially get rid of the issue workarounded in [1].
      
      [1] 28c015a9 ("mtd: davinci-nand: disable subpage write for keystone-nand")
      
      Fixes: 6a4123e5 ("mtd: nand: davinci_nand, 4-bit ECC for smallpage")
      Cc: <stable@vger.kernel.org>
      Signed-off-by: NKarl Beldan <kbeldan@baylibre.com>
      Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
      Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
      f6d7c1b5
  15. 06 5月, 2016 3 次提交
  16. 07 1月, 2016 2 次提交
  17. 19 12月, 2015 2 次提交
  18. 09 12月, 2015 1 次提交
  19. 12 11月, 2015 1 次提交
    • B
      mtd: nand: drop unnecessary partition parser data · a61ae81a
      Brian Norris 提交于
      All of these drivers set up a parser data struct just to communicate DT
      partition data. This field has been deprecated and is instead supported
      by telling nand_scan_ident() about the 'flash_node'.
      
      This patch:
       * sets chip->flash_node for those drivers that didn't already (but used
         OF partitioning)
       * drops the parser data
       * switches to the simpler mtd_device_register() where possible, now
         that we've eliminated one of the auxiliary parameters
      
      Now that we've assigned chip->flash_node for these drivers, we can
      probably rely on nand_dt_init() to do more of the DT parsing for us, but
      for now, I don't want to fiddle with each of these drivers. The parsing
      is done in duplicate for now on some drivers. I don't think this should
      break things. (Famous last words.)
      
      (Rolled in some changes by Boris Brezillon)
      Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
      Reviewed-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
      a61ae81a
  20. 14 10月, 2015 1 次提交