This blank line was introduced in commit c8521969 ("drm/panel:
simple: Add support for BOE TV080WUM-NL0"), likely by mistake.
Reviewed-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Both the Innolux ZJ070NA-01P and Samsung LTN101NT05 were listing the
horizontal and vertical resolutions in the size.width and size.height
fields, whereas they should contain the physical dimensions of the
panel.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add support for TPK U.S.A. LLC Fusion 7", 10.1" panels to the DRM simple
panel driver.
Signed-off-by: NBhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add support for the Innolux AT070TN92 panel.
Signed-off-by: NRiccardo Bortolato <bortolato@navaltechitalia.it>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

drm_display_mode_from_videomode() already calls drm_mode_set_name() on
the provided mode.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
[treding@nvidia.com: slightly reword commit message]
Signed-off-by: NThierry Reding <treding@nvidia.com>

All modes exposed by simple panels should be tagged as driver defined
modes. Moreover, if a panel supports only one mode, this mode is
obviously the preferred one.

Doing this also fix a problem occurring when a 'video=' parameter is
passed on the kernel command line. In some cases the user provided mode
will be preferred over the simple panel ones, which might result in
unpredictable behavior.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Tested-by: NNicolas Ferre <nicolas.ferre@atmel.com>
[treding@nvidia.com: reshuffle some code for consistency]
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add support for the Olimex LCD-OLinuXino-4.3TS panel to the DRM simple
panel driver.

It is a 480x272 panel connected through a 24-bits RGB interface.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

This is a basic TFT panel with a 40-pin FPC connector on it.  The
specification doesn't define timings, but the Adafruit instructions
were setting up 800x480 CVT.

v2: Add .bus_format and vsync/hsync flags.
Signed-off-by: NEric Anholt <eric@anholt.net>
Acked-by: NRob Herring <robh@kernel.org>
[treding@nvidia.com: keep entries properly sorted]
Signed-off-by: NThierry Reding <treding@nvidia.com>

The drivers current default configuration drives the pixel data
on rising edge of the pixel clock. However, most display sample
data on rising edge... This leads to color shift artefacts visible
especially at edges.

This patch changes the relevant defines to be useful and actually
set the bits, and changes pixel clock polarity to drive the pixel
data on falling edge by default. The patch also adds an explicit
pixel clock polarity flag to the display introduced with the driver
(NEC WQVGA "nec,nl4827hc19-05b") using the new bus_flags field to
retain the initial behavior.
Signed-off-by: NStefan Agner <stefan@agner.ch>

Introduce bus_flags to specify display bus properties like signal
polarities. This is useful for parallel display buses, e.g. to
specify the pixel clock or data enable polarity.
Suggested-by: NThierry Reding <thierry.reding@gmail.com>
Acked-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Acked-by: NManfred Schlaegl <manfred.schlaegl@gmx.at>
Acked-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: NStefan Agner <stefan@agner.ch>

Add support for United Radiant Technology UMSH-8596MD-xT 7.0" WVGA TFT
LCD panels in the simple-panel driver.
Signed-off-by: NMaciej S. Szmigiero <mail@maciej.szmigiero.name>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The LG lp120up1 TFT LCD panel with eDP interface is a 12.0" 1920x1280
panel, which can be supported by the simple panel driver.
Signed-off-by: NJitao Shi <jitao.shi@mediatek.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Set hsync/vsync to active low for g121x1_l03 panel to match the
recommended setting in the datasheet.
Signed-off-by: NAkshay Bhat <akshay.bhat@timesys.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The current default configuration is as follows:
- Invert VSYNC signal (active LOW)
- Invert HSYNC signal (active LOW)

The mode flags allow to specify the required polarity per
mode. Furthermore, none of the current driver settings is
actually a standard polarity.

This patch applies the current driver default polarities as
explicit flags to the display which has been introduced with
the driver (NEC WQVGA "nec,nl4827hc19-05b"). The driver now
also parses the flags field and applies the configuration
accordingly, by using the following values as standard
polarities: (e.g. when no flags are specified):
- VSYNC signal not inverted (active HIGH)
- HSYNC signal not inverted (active HIGH)
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStefan Agner <stefan@agner.ch>

The QiaoDian Xianshi QD43003C0-40 is a 4"3 TFT LCD panel.

Timings from the OTA5180A document, ver 0.9, section
10.1.1:
  http://www.orientdisplay.com/pdf/OTA5180A.pdfSigned-off-by: NJosh Wu <josh.wu@atmel.com>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Document that 'width' and 'height' are measured in millimeters.
Signed-off-by: NUlrich Ölmann <u.oelmann@pengutronix.de>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The Kyocera TCG121XGLP panel is an XGA LCD TFT panel connected through
LVDS, which can be supported by the simple panel driver.
Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add support for Innolux CheMei 12" G121X1-L03 XGA LVDS display.

Datasheet: http://www.azdisplays.com/PDF/G121X1-L03.pdfSigned-off-by: NAkshay Bhat <akshay.bhat@timesys.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The BOE TV080WUM-NL0 is an 8.0", 1200x1920 (WUXGA) TFT-LCD panel
connected using four DSI lanes. It can be supported by the simple-panel
driver.
Signed-off-by: NChris Zhong <zyw@rock-chips.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add support for the Okaya RS800480T-7X0GP to the DRM simple panel
driver.

The RS800480T-7X0GP is a WVGA (800x480) panel with an 18-bit parallel
LCD interface. It supports pixel clocks in the range of 30-40 MHz.

This panel details can be found at:
http://boundarydevices.com/product/7-800x480-display/Signed-off-by: NGary Bisson <gary.bisson@boundarydevices.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

This adds support for the NEC NL4827HC19-05B 480x272 panel to the DRM
simple panel driver.
Signed-off-by: NAlison Wang <b18965@freescale.com>
Signed-off-by: NXiubo Li <lixiubo@cmss.chinamobile.com>
Signed-off-by: NJianwei Wang <jianwei.wang.chn@gmail.com>
Acked-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
[treding@nvidia.com: add .bpc field for panel]
Signed-off-by: NThierry Reding <treding@nvidia.com>

The AUO B080UAN01 is an 8.0" WUXGA TFT LCD panel connected using four
DSI lanes. It can be supported by the simple-panel driver.
Signed-off-by: NThierry Reding <treding@nvidia.com>

According to the data sheet, the minimum horizontal blanking interval
is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
minimum working horizontal blanking interval to be 60 clocks.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The bus format both specifies the bpc and the way the individual bits get
serialized into the 7 LVDS timeslots.

While the is only one standard mapping for 6 bpc and so the driver could
infer the bit mapping from the bpc alone, there are more options for the
8 bpc case which makes specifiying the bus format mandatory.
To keep things consistent across panels and to set a precedent for new
panel additions add the proper bus format.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
Signed-off-by: NThierry Reding <treding@nvidia.com>

This patch adds the bus_format field to the HSD100PXN1 panel structure.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add support for the Hannstar HSD100PXN1 to the DRM simple panel driver.

The HSD100PXN1 is an XGA (1024x768) panel with an 18-bit LVDS interface.
It supports pixel clocks in the range of 55-75 MHz.

This panel is offered for sale by Freescale as a companion part to its'
i.MX5x Quick Start board and i.MX6 SABRE platforms with under the name
MCIMX-LVDS1.
Signed-off-by: NEric Nelson <eric.nelson@boundarydevices.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

This adds support for the LG LB070WV8 7" 800x480 panel to the DRM simple
panel driver.
Signed-off-by: NHeiko Schocher <hs@denx.de>
Signed-off-by: NThierry Reding <treding@nvidia.com>

This adds support for the AM-800480R3TMQW-A1H 7" 800x480 panel to the
DRM simple panel driver.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The HannStar HSD070PWW1 LVDS panel data sheet lists allowed ranges
additionally to the typical values for pixel clock rate (64.3-82 MHz)
and blanking intervals (54-681 clock cycles horizontally, 3-23 lines
vertically).

This patch replaces this panel's display mode with the display timing
information to describe acceptable timings. Since the HSYNC and VSYNC
are unused, the distribution between front porches, back porches, and
sync pulse lengths was chosen at will.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The simple panel driver's ->get_modes() implementation calculates the
display mode list from the typical timings and the ->get_timings()
implementation returns the timings to the connected encoder for mode
validation and fixup.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
[treding@nvidia.com: select VIDEOMODE_HELPERS]
Signed-off-by: NThierry Reding <treding@nvidia.com>

This adds support for the COM43H4M85ULC 3.7" 800x480 panel to the
DRM simple panel driver.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NThierry Reding <treding@nvidia.com>

This patch adds the bus_format field to the GPG482739QS5 panel structure.
Signed-off-by: NPhilipp Zabel <philipp.zabel@gmail.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The AUO b101ean01 panel is a 10.1" 1280x800 panel which can be supported
by the simple panel driver.
Signed-off-by: NHuang Lin <hl@rock-chips.com>
Reviewed-by: NDaniel Kurtz <djkurtz@chromium.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The Innolux ZJ070NA-01P is a 7.0" TFT LCD panel with an integrated LED
backlight unit.

This panel is used on the Technexion Toucan.
Signed-off-by: NMichael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The Innolux AT043TN24 4.3" WQVGA TFT LCD panel.
This panel with backlight is found in PDA 4.3" LCD screen (TM43xx series for
instance).
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The Shelly SCA07010-BFN-LNN is a 7.0" WVGA TFT LCD panel.
This panel with backlight is found in PDA 7" LCD screen (TM70xx series for
instance).
Signed-off-by: NBoris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

This panel is used by the Nyan Blaze board and can be supported by the
simple-panel driver.
Signed-off-by: NStéphane Marchesin <marcheu@chromium.org>
[tomeu.vizoso@collabora.com: add device tree binding document]
Signed-off-by: NTomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NAlexandre Courbot <acourbot@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The Shanghai AVIC Optoelectronics TM070DDH03 is a 7" 1024x600 TFT LCD
panel connecting to a 24-bit RGB LVDS interface.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NThierry Reding <treding@nvidia.com>

This patch adds support for the GiantPlus GPG48273QS5 4.3" WQVGA TFT LCD
panel to the simple-panel driver.

This panel is connected via a parallel bus and uses both HSYNC and
VSYNC, whose lengths are unfortunately not clearly defined. The
datasheet only specifies the front- and backporch length, but the timing
diagram suggests that both sync signals should be asserted for exactly
one clock cycle.
Signed-off-by: NPhilipp Zabel <philipp.zabel@gmail.com>
Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Foxlink's fl500wvr00-a0t supports RGB888 format.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: NThierry Reding <treding@nvidia.com>