1. 07 11月, 2012 1 次提交
  2. 29 10月, 2012 4 次提交
    • J
      zynq: move static peripheral mappings · f5800776
      Josh Cartwright 提交于
      Shifting them up into the vmalloc region prevents the following warning,
      when booting a zynq qemu target with more than 512mb of RAM:
      
        BUG: mapping for 0xe0000000 at 0xe0000000 out of vmalloc space
      
      In addition, it allows for reuse of these mappings when the proper
      drivers issue requests via ioremap().
      
      There are currently unknown issues with the early uart mapping.  For
      now, the uart will be mapped to a known working address.
      Signed-off-by: NJosh Cartwright <josh.cartwright@ni.com>
      Cc: John Linn <john.linn@xilinx.com>
      Acked-by: NArnd Bergmann <arnd@arndb.de>
      Tested-by: NMichal Simek <michal.simek@xilinx.com>
      f5800776
    • J
      zynq: remove use of CLKDEV_LOOKUP · f7977939
      Josh Cartwright 提交于
      The Zynq support in mainline does not (yet) make use of any of the
      generic clk or clk lookup functionality.  Remove what is upstream for
      now, until the out-of-tree implementation is in suitable form for
      merging.
      
      An important side effect of this patch is that it allows the building of
      a Zynq kernel without running into unresolved symbol problems:
      
         drivers/built-in.o: In function `amba_get_enable_pclk':
         clkdev.c:(.text+0x444): undefined reference to `clk_enable'
         drivers/built-in.o: In function `amba_remove':
         clkdev.c:(.text+0x488): undefined reference to `clk_disable'
         drivers/built-in.o: In function `amba_probe':
         clkdev.c:(.text+0x540): undefined reference to `clk_disable'
         drivers/built-in.o: In function `amba_device_add':
         clkdev.c:(.text+0x77c): undefined reference to `clk_disable'
         drivers/built-in.o: In function `enable_clock':
         clkdev.c:(.text+0x29738): undefined reference to `clk_enable'
         drivers/built-in.o: In function `disable_clock':
         clkdev.c:(.text+0x29778): undefined reference to `clk_disable'
         drivers/built-in.o: In function `__pm_clk_remove':
         clkdev.c:(.text+0x297f8): undefined reference to `clk_disable'
         drivers/built-in.o: In function `pm_clk_suspend':
         clkdev.c:(.text+0x29bc8): undefined reference to `clk_disable'
         drivers/built-in.o: In function `pm_clk_resume':
         clkdev.c:(.text+0x29c28): undefined reference to `clk_enable'
         make[2]: *** [vmlinux] Error 1
         make[1]: *** [sub-make] Error 2
         make: *** [all] Error 2
      
      In addition, eliminate Zynq's "use" of the versatile platform, as it is
      no longer needed.  As Nick Bowler points out:
      
         For the record, I think this was introduced by commit 56a34b03
         ("ARM: versatile: Make plat-versatile clock optional") which forgot to
         select PLAT_VERSATILE_CLOCK on Zynq.  This is not all that surprising,
         because the fact that Zynq "uses" PLAT_VERSATILE is secretly hidden in
         the Makefile.
      
         Nevertheless, the only feature from versatile that Zynq needed was the
         clock support, so this patch should *also* delete the secret use of
         plat-versatile by removing this line from arch/arm/Makefile:
      
            plat-$(CONFIG_ARCH_ZYNQ)      += versatile
      Signed-off-by: NJosh Cartwright <josh.cartwright@ni.com>
      Cc: John Linn <john.linn@xilinx.com>
      Acked-by: NArnd Bergmann <arnd@arndb.de>
      Tested-by: NMichal Simek <michal.simek@xilinx.com>
      f7977939
    • J
      zynq: use pl310 device tree bindings · 0fcfdbca
      Josh Cartwright 提交于
      The Zynq has a PL310 L2 cache controller.  Convert in-tree uses to using
      the device tree.
      Signed-off-by: NJosh Cartwright <josh.cartwright@ni.com>
      Cc: John Linn <john.linn@xilinx.com>
      Acked-by: NArnd Bergmann <arnd@arndb.de>
      Tested-by: NMichal Simek <michal.simek@xilinx.com>
      0fcfdbca
    • J
      zynq: use GIC device tree bindings · f447ed2d
      Josh Cartwright 提交于
      The Zynq uses the cortex-a9-gic.  This eliminates the need to hardcode
      register addresses.
      Signed-off-by: NJosh Cartwright <josh.cartwright@ni.com>
      Cc: John Linn <john.linn@xilinx.com>
      Acked-by: NArnd Bergmann <arnd@arndb.de>
      Tested-by: NMichal Simek <michal.simek@xilinx.com>
      f447ed2d
  3. 07 3月, 2012 1 次提交
  4. 22 2月, 2012 1 次提交
  5. 21 1月, 2012 1 次提交
  6. 05 1月, 2012 2 次提交
  7. 27 11月, 2011 1 次提交
  8. 16 11月, 2011 1 次提交
  9. 14 10月, 2011 1 次提交
  10. 26 9月, 2011 1 次提交
  11. 21 6月, 2011 1 次提交
    • J
      ARM: Xilinx: Adding Xilinx board support · b85a3ef4
      John Linn 提交于
      The 1st board support is minimal to get a system up and running
      on the Xilinx platform.
      
      This platform reuses the clock implementation from plat-versatile, and
      it depends entirely on CONFIG_OF support.  There is only one board
      support file which obtains all device information from a device tree
      dtb file which is passed to the kernel at boot time.
      Signed-off-by: NJohn Linn <john.linn@xilinx.com>
      b85a3ef4