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  1. 16 2月, 2019 2 次提交
  3. 14 2月, 2019 2 次提交
    • D
      net: dsa: bcm_sf2: potential array overflow in bcm_sf2_sw_suspend() · 8d6ea932
      由 Dan Carpenter 提交于 
      The value of ->num_ports comes from bcm_sf2_sw_probe() and it is less
than or equal to DSA_MAX_PORTS.  The ds->ports[] array is used inside
the dsa_is_user_port() and dsa_is_cpu_port() functions.  The ds->ports[]
array is allocated in dsa_switch_alloc() and it has ds->num_ports
elements so this leads to a static checker warning about a potential out
of bounds read.

Fixes: 8cfa9498 ("net: dsa: bcm_sf2: add suspend/resume callbacks")
Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: NVivien Didelot <vivien.didelot@gmail.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      8d6ea932
    • J
      dsa: mv88e6xxx: Ensure all pending interrupts are handled prior to exit · 7c0db24c
      由 John David Anglin 提交于 
      The GPIO interrupt controller on the espressobin board only supports edge interrupts.
If one enables the use of hardware interrupts in the device tree for the 88E6341, it is
possible to miss an edge.  When this happens, the INTn pin on the Marvell switch is
stuck low and no further interrupts occur.

I found after adding debug statements to mv88e6xxx_g1_irq_thread_work() that there is
a race in handling device interrupts (e.g. PHY link interrupts).  Some interrupts are
directly cleared by reading the Global 1 status register.  However, the device interrupt
flag, for example, is not cleared until all the unmasked SERDES and PHY ports are serviced.
This is done by reading the relevant SERDES and PHY status register.

The code only services interrupts whose status bit is set at the time of reading its status
register.  If an interrupt event occurs after its status is read and before all interrupts
are serviced, then this event will not be serviced and the INTn output pin will remain low.

This is not a problem with polling or level interrupts since the handler will be called
again to process the event.  However, it's a big problem when using level interrupts.

The fix presented here is to add a loop around the code servicing switch interrupts.  If
any pending interrupts remain after the current set has been handled, we loop and process
the new set.  If there are no pending interrupts after servicing, we are sure that INTn has
gone high and we will get an edge when a new event occurs.

Tested on espressobin board.

Fixes: dc30c35b ("net: dsa: mv88e6xxx: Implement interrupt support.")
Signed-off-by: NJohn David Anglin <dave.anglin@bell.net>
Tested-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      7c0db24c
  5. 08 2月, 2019 1 次提交
  7. 06 2月, 2019 1 次提交
  9. 28 1月, 2019 1 次提交
  11. 18 1月, 2019 1 次提交
  13. 11 1月, 2019 1 次提交
  15. 05 1月, 2019 2 次提交
  17. 28 12月, 2018 1 次提交
  19. 21 12月, 2018 1 次提交
    • T
      net: dsa: microchip: fix unicast frame leak · 962ad710
      由 Tristram Ha 提交于 
      Port partitioning is done by enabling UNICAST_VLAN_BOUNDARY and changing
the default port membership of 0x7f to other values such that there is
no communication between ports.  In KSZ9477 the member for port 1 is
0x41; port 2, 0x42; port 3, 0x44; port 4, 0x48; port 5, 0x50; and port 7,
0x60.  Port 6 is the host port.

Setting a zero value can be used to stop port from receiving.

However, when UNICAST_VLAN_BOUNDARY is disabled and the unicast addresses
are already learned in the dynamic MAC table, setting zero still allows
devices connected to those ports to communicate.  This does not apply to
multicast and broadcast addresses though.  To prevent these leaks and
make the function of port membership consistent UNICAST_VLAN_BOUNDARY
should never be disabled.

Note that UNICAST_VLAN_BOUNDARY is enabled by default in KSZ9477.

Fixes: b987e98e ("dsa: add DSA switch driver for Microchip KSZ9477")
Signed-off-by: NTristram Ha <Tristram.Ha@microchip.com>
Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      962ad710
  21. 20 12月, 2018 1 次提交
  23. 18 12月, 2018 1 次提交
  25. 17 12月, 2018 1 次提交
  27. 11 12月, 2018 1 次提交
  29. 04 12月, 2018 1 次提交
  31. 21 11月, 2018 6 次提交
  33. 16 11月, 2018 1 次提交
  35. 12 11月, 2018 6 次提交
  37. 08 11月, 2018 1 次提交
  39. 07 11月, 2018 5 次提交
  41. 03 11月, 2018 1 次提交
  43. 22 10月, 2018 2 次提交