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  1. 07 5月, 2020 9 次提交
  3. 04 5月, 2020 1 次提交
  5. 02 5月, 2020 3 次提交
  7. 30 4月, 2020 12 次提交
  9. 28 4月, 2020 2 次提交
  11. 27 4月, 2020 1 次提交
  13. 26 4月, 2020 2 次提交
    • T
      MIPS: Loongson: Add support for perf tool · e2e13925
      由 Tiezhu Yang 提交于 
      In order to use perf tool on the Loongson platform, we should enable kernel
support for various performance events provided by software and hardware,
so add CONFIG_PERF_EVENTS=y to loongson3_defconfig.

E.g. without this patch:

[loongson@localhost perf]$ ./perf list

List of pre-defined events (to be used in -e):

  duration_time                                      [Tool event]

  rNNN                                               [Raw hardware event descriptor]
  cpu/t1=v1[,t2=v2,t3 ...]/modifier                  [Raw hardware event descriptor]
   (see 'man perf-list' on how to encode it)

  mem:<addr>[/len][:access]                          [Hardware breakpoint]

With this patch:

[loongson@localhost perf]$ ./perf list

List of pre-defined events (to be used in -e):

  branch-instructions OR branches                    [Hardware event]
  branch-misses                                      [Hardware event]
  cpu-cycles OR cycles                               [Hardware event]
  instructions                                       [Hardware event]

  alignment-faults                                   [Software event]
  bpf-output                                         [Software event]
  context-switches OR cs                             [Software event]
  cpu-clock                                          [Software event]
  cpu-migrations OR migrations                       [Software event]
  dummy                                              [Software event]
  emulation-faults                                   [Software event]
  major-faults                                       [Software event]
  minor-faults                                       [Software event]
  page-faults OR faults                              [Software event]
  task-clock                                         [Software event]

  duration_time                                      [Tool event]

  L1-dcache-load-misses                              [Hardware cache event]
  L1-dcache-store-misses                             [Hardware cache event]
  L1-icache-load-misses                              [Hardware cache event]
  branch-load-misses                                 [Hardware cache event]
  branch-loads                                       [Hardware cache event]
  dTLB-load-misses                                   [Hardware cache event]
  dTLB-store-misses                                  [Hardware cache event]
  iTLB-load-misses                                   [Hardware cache event]

  rNNN                                               [Raw hardware event descriptor]
  cpu/t1=v1[,t2=v2,t3 ...]/modifier                  [Raw hardware event descriptor]
   (see 'man perf-list' on how to encode it)

  mem:<addr>[/len][:access]                          [Hardware breakpoint]
Signed-off-by: NTiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: NThomas Bogendoerfer <tsbogend@alpha.franken.de>
      e2e13925
    • H
      MIPS: Rename the "Fill" cache ops to avoid build failure · a44f8309
      由 Huacai Chen 提交于 
      MIPS define a "Fill" macro as a cache operation in cacheops.h, this
will cause build failure under some special configurations because in
seq_file.c there is a "Fill" label. To avoid this failure we rename the
"Fill" macro to "Fill_I" which has the same coding style as other cache
operations in cacheops.h (we think renaming the "Fill" macro is more
reasonable than renaming the "Fill" label).

Callers of "Fill" macro is also updated.
Signed-off-by: NHuacai Chen <chenhc@lemote.com>
Signed-off-by: NThomas Bogendoerfer <tsbogend@alpha.franken.de>
      a44f8309
  15. 25 4月, 2020 5 次提交
  17. 22 4月, 2020 1 次提交
  19. 21 4月, 2020 4 次提交
    • T
      MIPS: Make sparse_init() using top-down allocation · 269b3a9a
      由 Tiezhu Yang 提交于 
      In the current code, if CONFIG_SWIOTLB is set, when failed to get IO TLB
memory from the low pages by plat_swiotlb_setup(), it may lead to the boot
process failed with kernel panic.

(1) On the Loongson and SiByte platform
arch/mips/loongson64/dma.c
arch/mips/sibyte/common/dma.c
void __init plat_swiotlb_setup(void)
{
	swiotlb_init(1);
}

kernel/dma/swiotlb.c
void  __init
swiotlb_init(int verbose)
{
...
	vstart = memblock_alloc_low(PAGE_ALIGN(bytes), PAGE_SIZE);
	if (vstart && !swiotlb_init_with_tbl(vstart, io_tlb_nslabs, verbose))
		return;
...
	pr_warn("Cannot allocate buffer");
	no_iotlb_memory = true;
}

phys_addr_t swiotlb_tbl_map_single()
{
...
	if (no_iotlb_memory)
		panic("Can not allocate SWIOTLB buffer earlier ...");
...
}

(2) On the Cavium OCTEON platform
arch/mips/cavium-octeon/dma-octeon.c
void __init plat_swiotlb_setup(void)
{
...
	octeon_swiotlb = memblock_alloc_low(swiotlbsize, PAGE_SIZE);
	if (!octeon_swiotlb)
		panic("%s: Failed to allocate %zu bytes align=%lx\n",
		      __func__, swiotlbsize, PAGE_SIZE);
...
}

Because IO_TLB_DEFAULT_SIZE is 64M, if the rest size of low memory is less
than 64M when call plat_swiotlb_setup(), we can easily reproduce the panic
case.

In order to reduce the possibility of kernel panic when failed to get IO
TLB memory under CONFIG_SWIOTLB, it is better to allocate low memory as
small as possible before plat_swiotlb_setup(), so make sparse_init() using
top-down allocation.
Reported-by: NJuxin Gao <gaojuxin@loongson.cn>
Co-developed-by: NJuxin Gao <gaojuxin@loongson.cn>
Signed-off-by: NJuxin Gao <gaojuxin@loongson.cn>
Signed-off-by: NTiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: NThomas Bogendoerfer <tsbogend@alpha.franken.de>
      269b3a9a
    • T
      MIPS: Cleanup code about plat_mem_setup() · 2a3d47c9
      由 Tiezhu Yang 提交于 
      In the current code, plat_mem_setup() is called by arch_mem_init() instead
of setup_arch() and has been declared in asm/bootinfo.h, so modify the code
comment to reflect the reality and remove the useless duplicate declartion
in arch/mips/kernel/setup.c.
Signed-off-by: NTiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: NThomas Bogendoerfer <tsbogend@alpha.franken.de>
      2a3d47c9
    • T
      MIPS: Do not initialise globals to 0 · 2c66e281
      由 Tiezhu Yang 提交于 
      Fix the following checkpatch error:

ERROR: do not initialise globals to 0
#834: FILE: arch/mips/kernel/setup.c:834:
+int hw_coherentio = 0;	/* Actual hardware supported DMA coherency setting. */
Signed-off-by: NTiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: NThomas Bogendoerfer <tsbogend@alpha.franken.de>
      2c66e281
    • J
      MIPS: Loongson64: Mark RS780 HPET as broken · f46e1dc9
      由 Jiaxun Yang 提交于 
      This driver is using some dangerous hack to set MMIO address for HPET,
which might break systems with other kinds of PCH.

Also, as Loongson-3 cpufreq driver never appeared in mainline,
this driver rarely got used.

So we temporarily mark it as broken until we find a better solution.
Signed-off-by: NJiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: NThomas Bogendoerfer <tsbogend@alpha.franken.de>
      f46e1dc9