1. 02 11月, 2017 1 次提交
    • P
      irqchip: mips-gic: Use irq_cpu_online to (un)mask all-VP(E) IRQs · da61fcf9
      Paul Burton 提交于
      The gic_all_vpes_local_irq_controller chip currently attempts to operate
      on all CPUs/VPs in the system when masking or unmasking an interrupt.
      This has a few drawbacks:
      
       - In multi-cluster systems we may not always have access to all CPUs in
         the system. When all CPUs in a cluster are powered down that
         cluster's GIC may also power down, in which case we cannot configure
         its state.
      
       - Relatedly, if we power down a cluster after having configured
         interrupts for CPUs within it then the cluster's GIC may lose state &
         we need to reconfigure it. The current approach doesn't take this
         into account.
      
       - It's wasteful if we run Linux on fewer VPs than are present in the
         system. For example if we run a uniprocessor kernel on CPU0 of a
         system with 16 CPUs then there's no point in us configuring CPUs
         1-15.
      
       - The implementation is also lacking in that it expects the range
         0..gic_vpes-1 to represent valid Linux CPU numbers which may not
         always be the case - for example if we run on a system with more VPs
         than the kernel is configured to support.
      
      Fix all of these issues by only configuring the affected interrupts for
      CPUs which are online at the time, and recording the configuration in a
      new struct gic_all_vpes_chip_data for later use by CPUs being brought
      online. We register a CPU hotplug state (reusing
      CPUHP_AP_IRQ_GIC_STARTING which the ARM GIC driver uses, and which seems
      suitably generic for reuse with the MIPS GIC) and execute
      irq_cpu_online() in order to configure the interrupts on the newly
      onlined CPU.
      Signed-off-by: NPaul Burton <paul.burton@mips.com>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: linux-mips@linux-mips.org
      Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
      da61fcf9
  2. 26 9月, 2017 2 次提交
  3. 27 7月, 2017 2 次提交
  4. 25 7月, 2017 3 次提交
  5. 29 6月, 2017 1 次提交
  6. 23 6月, 2017 1 次提交
    • T
      genirq/cpuhotplug: Handle managed IRQs on CPU hotplug · c5cb83bb
      Thomas Gleixner 提交于
      If a CPU goes offline, interrupts affine to the CPU are moved away. If the
      outgoing CPU is the last CPU in the affinity mask the migration code breaks
      the affinity and sets it it all online cpus.
      
      This is a problem for affinity managed interrupts as CPU hotplug is often
      used for power management purposes. If the affinity is broken, the
      interrupt is not longer affine to the CPUs to which it was allocated.
      
      The affinity spreading allows to lay out multi queue devices in a way that
      they are assigned to a single CPU or a group of CPUs. If the last CPU goes
      offline, then the queue is not longer used, so the interrupt can be
      shutdown gracefully and parked until one of the assigned CPUs comes online
      again.
      
      Add a graceful shutdown mechanism into the irq affinity breaking code path,
      mark the irq as MANAGED_SHUTDOWN and leave the affinity mask unmodified.
      
      In the online path, scan the active interrupts for managed interrupts and
      if the interrupt is functional and the newly online CPU is part of the
      affinity mask, restart the interrupt if it is marked MANAGED_SHUTDOWN or if
      the interrupts is started up, try to add the CPU back to the effective
      affinity mask.
      Originally-by: NChristoph Hellwig <hch@lst.de>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Cc: Jens Axboe <axboe@kernel.dk>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Michael Ellerman <mpe@ellerman.id.au>
      Cc: Keith Busch <keith.busch@intel.com>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Link: http://lkml.kernel.org/r/20170619235447.273417334@linutronix.de
      c5cb83bb
  7. 26 5月, 2017 2 次提交
  8. 11 4月, 2017 1 次提交
  9. 04 4月, 2017 1 次提交
    • A
      perf: qcom: Add L3 cache PMU driver · 3071f13d
      Agustin Vega-Frias 提交于
      This adds a new dynamic PMU to the Perf Events framework to program
      and control the L3 cache PMUs in some Qualcomm Technologies SOCs.
      
      The driver supports a distributed cache architecture where the overall
      cache for a socket is comprised of multiple slices each with its own PMU.
      Access to each individual PMU is provided even though all CPUs share all
      the slices. User space needs to aggregate to individual counts to provide
      a global picture.
      
      The driver exports formatting and event information to sysfs so it can
      be used by the perf user space tools with the syntaxes:
         perf stat -a -e l3cache_0_0/read-miss/
         perf stat -a -e l3cache_0_0/event=0x21/
      Acked-by: NMark Rutland <mark.rutland@arm.com>
      Signed-off-by: NAgustin Vega-Frias <agustinv@codeaurora.org>
      [will: fixed sparse issues]
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      3071f13d
  10. 28 2月, 2017 1 次提交
  11. 09 2月, 2017 1 次提交
  12. 01 2月, 2017 2 次提交
    • T
      perf/x86/intel/uncore: Make package handling more robust · fff4b87e
      Thomas Gleixner 提交于
      The package management code in uncore relies on package mapping being
      available before a CPU is started. This changed with:
      
        9d85eb91 ("x86/smpboot: Make logical package management more robust")
      
      because the ACPI/BIOS information turned out to be unreliable, but that
      left uncore in broken state. This was not noticed because on a regular boot
      all CPUs are online before uncore is initialized.
      
      Move the allocation to the CPU online callback and simplify the hotplug
      handling. At this point the package mapping is established and correct.
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
      Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
      Cc: Jiri Olsa <jolsa@redhat.com>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Sebastian Siewior <bigeasy@linutronix.de>
      Cc: Stephane Eranian <eranian@google.com>
      Cc: Vince Weaver <vincent.weaver@maine.edu>
      Cc: Yasuaki Ishimatsu <yasu.isimatu@gmail.com>
      Fixes: 9d85eb91 ("x86/smpboot: Make logical package management more robust")
      Link: http://lkml.kernel.org/r/20170131230141.377156255@linutronix.deSigned-off-by: NIngo Molnar <mingo@kernel.org>
      fff4b87e
    • T
      perf/x86/intel/rapl: Make package handling more robust · dd86e373
      Thomas Gleixner 提交于
      The package management code in RAPL relies on package mapping being
      available before a CPU is started. This changed with:
      
        9d85eb91 ("x86/smpboot: Make logical package management more robust")
      
      because the ACPI/BIOS information turned out to be unreliable, but that
      left RAPL in broken state. This was not noticed because on a regular boot
      all CPUs are online before RAPL is initialized.
      
      A possible fix would be to reintroduce the mess which allocates a package
      data structure in CPU prepare and when it turns out to already exist in
      starting throw it away later in the CPU online callback. But that's a
      horrible hack and not required at all because RAPL becomes functional for
      perf only in the CPU online callback. That's correct because user space is
      not yet informed about the CPU being onlined, so nothing caan rely on RAPL
      being available on that particular CPU.
      
      Move the allocation to the CPU online callback and simplify the hotplug
      handling. At this point the package mapping is established and correct.
      
      This also adds a missing check for available package data in the
      event_init() function.
      Reported-by: NYasuaki Ishimatsu <yasu.isimatu@gmail.com>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
      Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
      Cc: Jiri Olsa <jolsa@redhat.com>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Sebastian Siewior <bigeasy@linutronix.de>
      Cc: Stephane Eranian <eranian@google.com>
      Cc: Vince Weaver <vincent.weaver@maine.edu>
      Fixes: 9d85eb91 ("x86/smpboot: Make logical package management more robust")
      Link: http://lkml.kernel.org/r/20170131230141.212593966@linutronix.deSigned-off-by: NIngo Molnar <mingo@kernel.org>
      dd86e373
  13. 16 1月, 2017 1 次提交
  14. 25 12月, 2016 7 次提交
  15. 15 12月, 2016 1 次提交
    • T
      clocksource/dummy_timer: Move hotplug callback after the real timers · 9bf11ecc
      Thomas Gleixner 提交于
      When the dummy timer callback is invoked before the real timer callbacks,
      then it tries to install that timer for the starting CPU. If the platform
      does not have a broadcast timer installed the installation fails with a
      kernel crash. The crash happens due to a unconditional deference of the non
      available broadcast device. This needs to be fixed in the timer core code.
      
      But even when this is fixed in the core code then installing the dummy
      timer before the real timers is a pointless exercise.
      
      Move it to the end of the callback list.
      
      Fixes: 00c1d17a ("clocksource/dummy_timer: Convert to hotplug state machine")
      Reported-and-tested-by: NMason <slash.tmp@free.fr>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: Anna-Maria Gleixner <anna-maria@linutronix.de>
      Cc: Richard Cochran <rcochran@linutronix.de>
      Cc: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
      Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
      Cc: Peter Zijlstra <peterz@infradead.org>,
      Cc: Sebastian Frias <sf84@laposte.net>
      Cc: Thibaud Cornic <thibaud_cornic@sigmadesigns.com>
      Cc: Robin Murphy <robin.murphy@arm.com>
      Link: http://lkml.kernel.org/r/1147ef90-7877-e4d2-bb2b-5c4fa8d3144b@free.fr
      9bf11ecc
  16. 02 12月, 2016 8 次提交
  17. 23 11月, 2016 5 次提交