提交 · da483dd1d8d7bdfd64192a1df8e7b6a7a8b2b7f2 · openeuler / Kernel

01 7月, 2020 40 次提交

drm/amd/powerplay: use existed smu_dpm_set* interfaces to implement powergate functions · da483dd1

由 Huang Rui 提交于 6月 01, 2020

Abstract powergate_vcn/jpeg functions, using smu_dpm_set* to implement it.
Signed-off-by: NHuang Rui <ray.huang@amd.com>
Reviewed-by: NKevin Wang <kevin1.wang@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

da483dd1

drm/amdgpu: temporarily read bounding box from gpu_info fw for navi12 · cc375d8c

由 Tianci.Yin 提交于 6月 03, 2020

The bounding box is still needed by Navi12, temporarily read it from gpu_info
firmware. Should be droped when DAL no longer needs it.
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: NXiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: NFeifei Xu <Feifei.Xu@amd.com>
Signed-off-by: NTianci.Yin <tianci.yin@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

cc375d8c

drm/amd/display: Add DCN3 to Kconfig · 96134346

由 Bhawanpreet Lakha 提交于 5月 21, 2020

Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

96134346

drm/amd/display: Add DCN3 blocks to Makefile · e77165bf

由 Bhawanpreet Lakha 提交于 5月 25, 2020

Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

e77165bf

drm/amdgpu/display: fix build without CONFIG_DRM_AMD_DC_DCN3_0 · cb8bcc98

由 Alex Deucher 提交于 6月 03, 2020

Need to guard some new DCN3.0 stuff.
Reviewed-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

cb8bcc98

drm/amd/display: fix and simplify pipe split logic for DCN3 · f0bfa78b

由 Dmytro Laktyushkin 提交于 4月 27, 2020

This was done already done for other DCN blocks.
Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

f0bfa78b

drm/amdgpu: Enable DM block for DCN3 · 464ab91a

由 Bhawanpreet Lakha 提交于 5月 21, 2020

Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

464ab91a

drm/amd/display: Remove Unused Registers · 7f3e2919

由 Bhawanpreet Lakha 提交于 5月 21, 2020

Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

7f3e2919

drm/amd/display: Handle RGBE_ALPHA Pixel Format · fb625e1b

由 Bhawanpreet Lakha 提交于 5月 21, 2020

Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

fb625e1b

drm/amd/display: Init function tables for DCN3 · c5c76abd

由 Bhawanpreet Lakha 提交于 5月 25, 2020

Initilize function tables for hw programing
Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

c5c76abd

drm/amd/display: Add DCN3 VPG · 3c10f4fb

由 Bhawanpreet Lakha 提交于 5月 25, 2020

Video Package generator.

used to prepare avi info, DP info etc
Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

3c10f4fb

drm/amd/display: Add DCN3 AFMT · 73de3de5

由 Bhawanpreet Lakha 提交于 5月 21, 2020

Audio formating

Audio related code for setup/control
Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

73de3de5

drm/amd/display: Add DCN3 Command Table Helpers · 330fa233

由 Bhawanpreet Lakha 提交于 5月 21, 2020

-Handle DCN3 cases for bios parser and command tables
-Add command function tables for DCN3
Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

330fa233

drm/amd/display: Add DCN3 Resource · 5dba4991

由 Bhawanpreet Lakha 提交于 5月 21, 2020

Add support for managing resources for DCN3
Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

5dba4991

drm/amd/display: Add DCN3 Support in DM (v2) · 79037324

由 Bhawanpreet Lakha 提交于 5月 21, 2020

Handle DCN3 in amdgpu_dm

v2: fix num_pkrs handling
Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

79037324

drm/amd/display: Add DCN3 HWSEQ · d99f1387

由 Bhawanpreet Lakha 提交于 5月 21, 2020

Add HW sequence programing for DCN3
Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

d99f1387

drm/amd/display: Add DCN3 DMUB · 5baebf61

由 Bhawanpreet Lakha 提交于 5月 29, 2020

DMUB (Display Micro-Controller Unit)

Used to read/write regs
Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

5baebf61

drm/amd/display: Add DCN3 GPIO · 666ed8bf

由 Bhawanpreet Lakha 提交于 5月 21, 2020

Add support to program GPIO HW block
Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

666ed8bf

drm/amd/display: Add DCN3 IRQ · 21f4809a

由 Bhawanpreet Lakha 提交于 5月 21, 2020

Add IWQ services for DCN3,

This allows us to create/init and manage irqs for DCN3
Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

21f4809a

drm/amd/display: Add DCN3 DML · 6725a88f

由 Bhawanpreet Lakha 提交于 5月 21, 2020

Add support for DML(Display mode library) for bandwidth calculations
Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

6725a88f

drm/amd/display: Add DCN3 DWB · 8993dee0

由 Bhawanpreet Lakha 提交于 5月 21, 2020

Add support to program the DCN3 DWB (Display Writeback)

HW Blocks:

 +--------++------+       +----------+
 | HUBBUB || HUBP |  <--  | MMHUBBUB |
 +--------++------+       +----------+
        |                     ^
        v                     |
    +--------+            +--------+
    |  DPP   |            |  DWB   |
    +--------+            +--------+
        |
        v                      ^
    +--------+                 |
    |  MPC   |                 |
    +--------+                 |
        |                      |
        v                      |
    +-------+                  |
    |  OPP  |                  |
    +-------+                  |
        |                      |
        v                      |
    +--------+                /
    |  OPTC  |  --------------
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+
Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

8993dee0

drm/amd/display: Add DCN3 MMHUBHUB · 4898dc48

由 Bhawanpreet Lakha 提交于 5月 21, 2020

Add support to program the DCN3 MMHUBBUB (Multimedia HUB interface)

HW Blocks:

 +--------++------+       +----------+
 | HUBBUB || HUBP |  <--  | MMHUBBUB |
 +--------++------+       +----------+
        |
        v
    +--------+
    |  DPP   |
    +--------+
        |
        v
    +--------+
    |  MPC   |
    +--------+
        |
        v
    +-------+
    |  OPP  |
    +-------+
        |
        v
    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+
Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

4898dc48

drm/amd/display: Add DCN3 HUBP · db7b0216

由 Bhawanpreet Lakha 提交于 5月 21, 2020

Add support to program the DCN3 HUBP (Display to data fabric interface
pipe)

HW Blocks:

 +--------++------+
 | HUBBUB || HUBP |
 +--------++------+
        |
        v
    +--------+
    |  DPP   |
    +--------+
        |
        v
    +--------+
    |  MPC   |
    +--------+
        |
        v
    +-------+
    |  OPP  |
    +-------+
        |
        v
    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+
Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

db7b0216

drm/amd/display: Add DCN3 HUBHUB · 8f712e3e

由 Bhawanpreet Lakha 提交于 5月 21, 2020

Add support to program the HUBBUB (DCN memory HUB interface)

HW Blocks:

 +--------+
 | HUBBUB |
 +--------+
        |
        v
    +--------+
    |  DPP   |
    +--------+
        |
        v
    +--------+
    |  MPC   |
    +--------+
        |
        v
    +-------+
    |  OPP  |
    +-------+
        |
        v
    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+
Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

8f712e3e

drm/amd/display: Add DCN3 DPP · 03f54d7d

由 Bhawanpreet Lakha 提交于 5月 21, 2020

Add support to program the DCN3 DPP (Multiple pipe and plane combine)

HW Blocks:

    +--------+
    |  DPP   |
    +--------+
        |
        v
    +--------+
    |  MPC   |
    +--------+
        |
        v
    +-------+
    |  OPP  |
    +-------+
        |
        v
    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+
Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

03f54d7d

drm/amd/display: Add DCN3 MPC · b708205f

由 Bhawanpreet Lakha 提交于 5月 21, 2020

Add support to program the DCN3 MPC (Multiple pipe and plane combine)

HW Blocks:

    +--------+
    |  MPC   |
    +--------+
        |
        v
    +-------+
    |  OPP  |
    +-------+
        |
        v
    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+
Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

b708205f

drm/amd/display: Add DCN3 OPP header · 8ea13e52

由 Bhawanpreet Lakha 提交于 5月 22, 2020

Add support to program the DCN3 OPP (Output Plane Processing)

HW Blocks:

    +-------+
    |  OPP  |
    +-------+
        |
        v
    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+
Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

8ea13e52

drm/amd/display: Add DCN3 OPTC · 64e7f91e

由 Bhawanpreet Lakha 提交于 5月 21, 2020

Add support for programming the DCN3 OPTC (Output Timing Controller)

HW Blocks:

    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+
Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

64e7f91e

drm/amd/display: Add DCN3 DCCG · 2a3a0d5d

由 Bhawanpreet Lakha 提交于 5月 21, 2020

Add programming of the DCCG (Display Controller Clock Generator)
block:

HW Blocks:

    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+
Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

2a3a0d5d

drm/amd/display: Add DCN3 CLK_MGR · 4d55b0dd

由 Bhawanpreet Lakha 提交于 5月 21, 2020

Adds support for handling of clocking relevant to the DCN3 block
Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

4d55b0dd

drm/amd/display: Add DCN3 DIO · be547111

由 Bhawanpreet Lakha 提交于 5月 22, 2020

Add support for the DIO (Display IO)  block of DCN3, which entails our
stream and link encoders.

HW Blocks:

    +--------+
    |  DIO   |
    +--------+
Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

be547111

drm/amd/display: Add DCN3 chip ids · 7c40270b

由 Bhawanpreet Lakha 提交于 5月 21, 2020

Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

7c40270b

drm/amdgpu: bypass tmr when reserve c2p memory · 2c6e83a1

由 Likun Gao 提交于 5月 26, 2020

C2P memory reserved should not in tmr memory range.
Signed-off-by: NLikun Gao <Likun.Gao@amd.com>
Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

2c6e83a1

drm/amdgpu: remove unnecessary check for mem train · 72d208c2

由 Likun Gao 提交于 5月 22, 2020

a.Check whether mem train support when try to reserve related memory.
b.Remove ASIC check and atom firmware table version check as the check
of firmware capability is enough to achieve that purpose.
Signed-off-by: NLikun Gao <Likun.Gao@amd.com>
Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

72d208c2

drm/amdgpu: support memory training for sienna_cichlid · 0a4fa83c

由 Likun Gao 提交于 5月 21, 2020

Add memory training support for sienna_cichlid.
Signed-off-by: NLikun Gao <Likun.Gao@amd.com>
Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

0a4fa83c

drm/amdgpu: reserve fb according to return value from vbios · 83d7f66a

由 Likun Gao 提交于 5月 21, 2020

Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards
for all the use cases (IP discovery/G6 memory
training/profiling/diagnostic data.etc), otherwise, fallback to legacy
approach to check and reserve tmr block for ip discovery data and G6
memory training data respectively
Signed-off-by: NLikun Gao <Likun.Gao@amd.com>
Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

83d7f66a

drm/amd/powerplay: let PMFW to handle the features disablement on BACO in V2 · 4c301044

由 Evan Quan 提交于 5月 29, 2020

For Sienna_Cichlid, PMFW will handle the features disablement on BACO in. No
need to have driver stepped in.

V2: limit this for baco really
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NLikun Gao <Likun.Gao@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

4c301044

drm/amd/powerplay: drop sienna_cichlid hardcode of using pptable · e2c14b2c

由 Likun Gao 提交于 5月 18, 2020

Drop the hardcode of sienna_cichlid which will force to use softpptable,
so that it can use pptable on vbios once the value of pp_table_id get
from vbios is 0.
Signed-off-by: NLikun Gao <Likun.Gao@amd.com>
Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

e2c14b2c

drm/amd/powerplay: update smu function for sienna_cichlid · 40d3b8db

由 Likun Gao 提交于 5月 13, 2020

Add function to check whether baco is support for sienna cichlid.
Remove fucntion of get clock by type with latency as it will not be
called.
Signed-off-by: NLikun Gao <Likun.Gao@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

40d3b8db

drm/amdgpu: update golden setting for sienna_cichlid · 04af75ef

由 Likun Gao 提交于 5月 08, 2020

Update golden setting for sienna_cichlid.
Signed-off-by: NLikun Gao <Likun.Gao@amd.com>
Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

04af75ef

openeuler / Kernel 接近 2 年 前同步成功

openeuler / Kernel
接近 2 年前同步成功