1. 07 1月, 2021 3 次提交
  2. 12 12月, 2020 1 次提交
    • M
      KVM: mmu: Fix SPTE encoding of MMIO generation upper half · 34c0f6f2
      Maciej S. Szmigiero 提交于
      Commit cae7ed3c ("KVM: x86: Refactor the MMIO SPTE generation handling")
      cleaned up the computation of MMIO generation SPTE masks, however it
      introduced a bug how the upper part was encoded:
      SPTE bits 52-61 were supposed to contain bits 10-19 of the current
      generation number, however a missing shift encoded bits 1-10 there instead
      (mostly duplicating the lower part of the encoded generation number that
      then consisted of bits 1-9).
      
      In the meantime, the upper part was shrunk by one bit and moved by
      subsequent commits to become an upper half of the encoded generation number
      (bits 9-17 of bits 0-17 encoded in a SPTE).
      
      In addition to the above, commit 56871d44 ("KVM: x86: fix overlap between SPTE_MMIO_MASK and generation")
      has changed the SPTE bit range assigned to encode the generation number and
      the total number of bits encoded but did not update them in the comment
      attached to their defines, nor in the KVM MMU doc.
      Let's do it here, too, since it is too trivial thing to warrant a separate
      commit.
      
      Fixes: cae7ed3c ("KVM: x86: Refactor the MMIO SPTE generation handling")
      Signed-off-by: NMaciej S. Szmigiero <maciej.szmigiero@oracle.com>
      Message-Id: <156700708db2a5296c5ed7a8b9ac71f1e9765c85.1607129096.git.maciej.szmigiero@oracle.com>
      Cc: stable@vger.kernel.org
      [Reorganize macros so that everything is computed from the bit ranges. - Paolo]
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      34c0f6f2
  3. 01 12月, 2020 1 次提交
  4. 29 11月, 2020 1 次提交
  5. 26 11月, 2020 4 次提交
  6. 25 11月, 2020 1 次提交
  7. 19 11月, 2020 4 次提交
  8. 16 11月, 2020 1 次提交
    • M
      xtensa: fix TLBTEMP area placement · 481535c5
      Max Filippov 提交于
      fast_second_level_miss handler for the TLBTEMP area has an assumption
      that page table directory entry for the TLBTEMP address range is 0. For
      it to be true the TLBTEMP area must be aligned to 4MB boundary and not
      share its 4MB region with anything that may use a page table. This is
      not true currently: TLBTEMP shares space with vmalloc space which
      results in the following kinds of runtime errors when
      fast_second_level_miss loads page table directory entry for the vmalloc
      space instead of fixing up the TLBTEMP area:
      
       Unable to handle kernel paging request at virtual address c7ff0e00
        pc = d0009275, ra = 90009478
       Oops: sig: 9 [#1] PREEMPT
       CPU: 1 PID: 61 Comm: kworker/u9:2 Not tainted 5.10.0-rc3-next-20201110-00007-g1fe4962fa983-dirty #58
       Workqueue: xprtiod xs_stream_data_receive_workfn
       a00: 90009478 d11e1dc0 c7ff0e00 00000020 c7ff0000 00000001 7f8b8107 00000000
       a08: 900c5992 d11e1d90 d0cc88b8 5506e97c 00000000 5506e97c d06c8074 d11e1d90
       pc: d0009275, ps: 00060310, depc: 00000014, excvaddr: c7ff0e00
       lbeg: d0009275, lend: d0009287 lcount: 00000003, sar: 00000010
       Call Trace:
         xs_stream_data_receive_workfn+0x43c/0x770
         process_one_work+0x1a1/0x324
         worker_thread+0x1cc/0x3c0
         kthread+0x10d/0x124
         ret_from_kernel_thread+0xc/0x18
      
      Cc: stable@vger.kernel.org
      Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      481535c5
  9. 13 11月, 2020 3 次提交
  10. 12 11月, 2020 2 次提交
  11. 11 11月, 2020 4 次提交
  12. 10 11月, 2020 4 次提交
  13. 08 11月, 2020 2 次提交
  14. 07 11月, 2020 2 次提交
  15. 06 11月, 2020 1 次提交
  16. 04 11月, 2020 6 次提交