mmhub ras is always owned by gpu driver. ras_funcs
initialization shall be done at ip level, instead of
putting it in common gmc interface file
Signed-off-by: NHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: NLijo Lazar <lijo.lazar@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Remove an unused function. Mapping the fbdev framebuffer is apparently
not supported.
Signed-off-by: NThomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This reverts commit f4a9be99.

The original commit was found to cause the following two issues
on sienna cichlid:
1. Refresh rate locked during vrrdemo
2. Display sticks on flipped landscape mode after changing
   orientation, and cannot be changed back to regular landscape
Signed-off-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Reviewed-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

DC version 3.2.130 brings improvements in multiple areas.
In summary, we highlight:

- Firmware release 0.0.59
- Fixes on display experiences for 4k TVs, register mask missing, etc.
- Enhancements on MST, code cleaning and debug messages.
Signed-off-by: NAric Cyr <aric.cyr@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[How&Why]
add params to send FEC status to firmware
Signed-off-by: NAnthony Koo <Anthony.Koo@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
Pipe input DSC bpc has a type mismatch with maximum DSC
input bpc - align the maximum with the pipe input type,
unsigned integer.

When checking the type we shoudl also check for an
implicit value of 0 and align with what the spreadsheet
does - default to max.

Rename output_bpc to dsc_input_bpc to reflect what the
field is actually used for.
Signed-off-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[WHY]
When on the desktop freesync is not enabled,
doing a frame stretch causes the TV to display
undesired output.

[HOW]
By changing the logic so that when ever fresync
is supported the TV is notified we are in fressync
instead on a non fresync state.
Signed-off-by: NHarry VanZyllDeJong <hvanzyll@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NAnthony Koo <Anthony.Koo@amd.com>
Acked-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why&How]
The driver always wants to synchronize streams
to the first edge of master's vsync pulse.
In order to determine that we can read timing
flags that are used to program vsync.

Master stream's vsync polarity - Multi Display Stream Synchronization edge:

        Negative               -              Falling Edge

        Positive               -              Rising Edge
Signed-off-by: NMikita Lipski <mikita.lipski@amd.com>
Reviewed-by: NSun peng Li <Sunpeng.Li@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Need to be able to trigger software hotplug for MST connectors

[How]
For unplug the driver calls to disable topologies manager
that connector is attached to. For plugging in it does the
whole rediscovery of all connectors in drm device and enbles their
topologies if attached.

The interface for MST connectors works in the following way:

1. To disconnect all MST topologies currently connected:
   echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst

2. To reconnect/rediscover all topologies that are physically
connected to the card:
   echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst

A related fix which has been merged with this patch
Leo Ma(Hanghong Ma)'s work:

Set power states before disable MST topology
[Why]
	When we try to disable MST topology from the
	debugfs entry, some receiver will hang.
[How]
	Set DPCD 600h power states to
	2(power down mode)before disable MST topology.
Signed-off-by: NMikita Lipski <mikita.lipski@amd.com>
Reviewed-by: NSun peng Li <Sunpeng.Li@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why/how]
Skip logic that sets preffered link settings
and just retrain with new link_settings from Debugfs
Signed-off-by: NMikita Lipski <mikita.lipski@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
DCN3 is not reusing DCN1 mask_sh_list, causing
SURFACE_FLIP_INT_MASK missing in the mapping.

[How]
Add the corresponding entry to DCN3 list.
Signed-off-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Commit 1c85f3db
("drm/amd/display: Add kernel doc to crc_rd_wrk
field") adds kernel doc for crc_rd_wrk field in
amdgpu_dm.h but it's incorrectly formatted.
Make htmldocs warns:

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:398: warning:
Incorrect use of kernel-doc format:          * @crc_rd_wrk

[How]
Tweak the kernel doc for crc_rd_wrk.

Fixes: 1c85f3db ("drm/amd/display: Add kernel doc to crc_rd_wrk field")
Signed-off-by: NWayne Lin <Wayne.Lin@amd.com>
Reviewed-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why/how]
Due to compiler optimization the values would be
passed to the division function uninitialized
causing a div by zero. Initialize the numerator
and denominator to 0 and 1 to prevent division
by zero.
Signed-off-by: NMikita Lipski <mikita.lipski@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
Currently to view the DCC_EN bit the entire DTN log
must be dumped. A compact method to view the DCC_EN
bit is desirable.

[how]
Introduce new debugfs interface that only dumps the
DCC_EN bit.

Example usage:
cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en
Signed-off-by: NVictor Lu <victorchengchi.lu@amd.com>
Reviewed-by: NHarry Wentland <Harry.Wentland@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why&How]
Add debug flag for an option to disable min fclk.
Signed-off-by: NHarry Wentland <harry.wentland@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why&How]
Add debug prints for SMU messages with regard to
versions, clocks, and more.
Signed-off-by: NHarry Wentland <harry.wentland@amd.com>
Reviewed-by: NRobin Singh <Robin.Singh@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
We need to keep track of the number of eDP links to
properly enumerate edp panel control instance.

[How]
Added dc_edp_id_count to dc_context to keep track of
number of eDP links.
Signed-off-by: NJake Wang <haonan.wang2@amd.com>
Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Functionality of LTTPR is reporter through the DPCD register

[How]
Expose a interface in debugfs to read the current status of
LTTPR as reported from the device's DPCD register
Signed-off-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]

The OTG_VUPDATE_KEEPOUT register and fields is
available on DCN10, and named the same in DCN20.

[How]

Move register definition and programming function
to dcn10 optc.

There is no functional change.
Signed-off-by: NLeo Li <sunpeng.li@amd.com>
Reviewed-by: NHarry Wentland <Harry.Wentland@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
There is case when the userspace like IGT test updates the custom
timings, i.e. the number of active lines CRTC property value,
and without committing the change, followed by
resetting the display, creating FB and plane to the pipe
and committing. The NULL pointer of pipe_ctx->plane_state
occurs and result in kernel crash. We need to avoid that.

[how]
add pointer check for the dc_plane_state of the pipe context in
the call of committing planes for stream in DC component.
Signed-off-by: NRobin Singh <robin.singh@amd.com>
Reviewed-by: NHarry Wentland <Harry.Wentland@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
     In MST setup, we'd use MST downstream AUX to
     dump the DPRX CRCs from sink device.

[how]
     Assign the mst_port->aux to read DPCD registers.
Signed-off-by: NDavid (Dingchen) Zhang <dingchen.zhang@amd.com>
Reviewed-by: NHarry Wentland <Harry.Wentland@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Today a parameter is passed to dmub_srv_send_gpint_command
which specifies the max amount of time to wait for the command
to be acked.
This parameter instead specifies the number of times to check if
the command was acked.
We wish to add a lower bound to the timeout, which can be
accomplished by using a delay or a timestamp.
It has been decided to use udelay instead of a timestamp simply
because we don't want to expose a high precision counter if it
doesn't yield large benefits.

[How]
Add udelay(1) between each for loop iteration.
Signed-off-by: NWyatt Wood <wyatt.wood@amd.com>
Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
GPINT command to get PSR state from FW times out.

[How]
Add retry to get valid PSR state.
Signed-off-by: NWyatt Wood <wyatt.wood@amd.com>
Reviewed-by: NAnthony Koo <Anthony.Koo@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

gfx ras is only available in cerntain ip generations.
Signed-off-by: NHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: NDennis Li <Dennis.Li@amd.com>
Reviewed-by: NJohn Clements <John.Clements@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

mmhub ras is only avaiable in cerntain mmhub ip
generation.
Signed-off-by: NHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: NDennis Li <Dennis.Li@amd.com>
Reviewed-by: NJohn Clements <John.Clements@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

df/mca ras is not managed by gpu driver when gpu
is connected to cpu through xgmi. gpu driver should
register x86 mca notifier for umc ras error
notification
Signed-off-by: NHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: NDennis Li <Dennis.Li@amd.com>
Reviewed-by: NJohn Clements <John.Clements@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

umc ras is not managed by gpu driver when gpu is
connected to cpu through xgmi. split umc callbacks
into ras and non-ras ones so gpu driver only
initializes umc ras callbacks when it manages
umc ras.
Signed-off-by: NHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: NDennis Li <Dennis.Li@amd.com>
Reviewed-by: NJohn Clements <John.Clements@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

xgmi ras is not managed by gpu driver when gpu is
connected to cpu through xgmi. move all xgmi ras
functions to xgmi_ras_funcs so gpu driver only
initializes xgmi ras functions when it manages
xgmi ras.
Signed-off-by: NHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: NDennis Li <Dennis.Li@amd.com>
Reviewed-by: NJohn Clements <John.Clements@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

nbio ras is not managed by gpu driver when gpu is
connected to cpu through xgmi. split nbio callbacks
into ras and non-ras ones so gpu driver only
initializes nbio ras callbacks when it manages
nbio ras.
Signed-off-by: NHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: NDennis Li <Dennis.Li@amd.com>
Reviewed-by: NJohn Clements <John.Clements@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

query_ras_error_address will be invoked to query bad
page address when there is poison data in HBM consumed
by GPU engines.
Signed-off-by: NHawking Zhang <Hawking.Zhang@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: NJohn Clements <John.Clements@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

umc query_ras_error_count will be invoked to query
umc correctable and uncorrectable error. It will
reset the umc ras error counter after the query.
Signed-off-by: NHawking Zhang <Hawking.Zhang@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: NJohn Clements <John.Clements@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Add helper functions to query correctable and
uncorrectable umc ras error.
Signed-off-by: NHawking Zhang <Hawking.Zhang@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: NJohn Clements <John.Clements@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

umc_v6_7_funcs are callbacks to support umc ras
functionalities in aldebaran
Signed-off-by: NHawking Zhang <Hawking.Zhang@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: NJohn Clements <John.Clements@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Driver only manages GFX/SDMA/MMHUB RAS in platforms
that gpu node is connected to cpu through XGMI, other
than that, it queries VBIOS for RAS capabilities.
Signed-off-by: NHawking Zhang <Hawking.Zhang@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: NJohn Clements <John.Clements@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Power Management IP is initialized/enabled before KFD init. When a
thermal throttling happens before kfd_smi_init is done, calling the KFD
SMI update function causes a stack dump by referring a NULL pointer (
smi_clients list). Check if kfd_init is completed before calling the
function.
Signed-off-by: NAmber Lin <Amber.Lin@amd.com>
Reviewed-by: NMukul Joshi <mukul.joshi@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

struct mod_hdcp is declared twice. One is declared at 33rd line.
The blew one is not needed. Remove the duplicate.
Signed-off-by: NWan Jiabing <wanjiabing@vivo.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

These were leftover from the old CI dpm code which was
retired a while ago.
Acked-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Fix patch check warning:
WARNING: suspect code indent for conditional statements (8, 17)
+       if (obj && obj->use < 0) {
+                DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name);

WARNING: braces {} are not necessary for single statement blocks
+       if (obj && obj->use < 0) {
+                DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name);
+       }
Signed-off-by: NBernard Zhao <bernard@vivo.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Fix patch check warning:
WARNING: Prefer kmalloc_array over kmalloc with multiply
+	buf = kmalloc(MAX_KFIFO_SIZE * sizeof(*buf), GFP_KERNEL);
Signed-off-by: NBernard Zhao <bernard@vivo.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NStanley.Yang <Stanley.Yang@amd.com>
Reivewed-by: NDennis Li <Dennis.Li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>