- 19 2月, 2022 5 次提交
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由 Yifan Zhang 提交于
Enabl psp support for psp 13.0.5. Signed-off-by: NYifan Zhang <yifan1.zhang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NHuang Rui <ray.huang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Yifan Zhang 提交于
this patch adds smuio support for smuio 13.0.10. Signed-off-by: NYifan Zhang <yifan1.zhang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NHuang Rui <ray.huang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Yifan Zhang 提交于
this patch adds support for nbio 7.3.0. Signed-off-by: NYifan Zhang <yifan1.zhang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NHuang Rui <ray.huang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Boyuan Zhang 提交于
Load VCN FW, set caps. Signed-off-by: NBoyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NHuang Rui <ray.huang@amd.com> Signed-off-by: NYifan Zhang <yifan1.zhang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NHuang Rui <ray.huang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Yifan Zhang 提交于
This patch adds support for sdma 5.2.6. Signed-off-by: NYifan Zhang <yifan1.zhang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NHuang Rui <ray.huang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 18 2月, 2022 6 次提交
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由 Yifan Zhang 提交于
this patch adds gc 10.3.6 support. Signed-off-by: NYifan Zhang <yifan1.zhang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NHuang Rui <ray.huang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Yifan Zhang 提交于
this patch adds support for gmc10. Signed-off-by: NYifan Zhang <yifan1.zhang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NHuang Rui <ray.huang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Yifan Zhang 提交于
This patch adds add nv common init for gc 10.3.6. Signed-off-by: NYifan Zhang <yifan1.zhang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NHuang Rui <ray.huang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Luben Tuikov 提交于
Dynamically initialize IP instance attributes. This eliminates bugs stemming from adding new attributes to an IP instance. Cc: Alex Deucher <Alexander.Deucher@amd.com> Reported-by: NTom StDenis <tom.stdenis@amd.com> Fixes: 4d7ba312 ("drm/amdgpu: Add "harvest" to IP discovery sysfs") Signed-off-by: NLuben Tuikov <luben.tuikov@amd.com> Acked-by: NAlex Deucher <Alexander.Deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Luben Tuikov 提交于
Fix this ARM warning: drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c:664:35: warning: format '%ld' expects argument of type 'long int', but argument 4 has type 'size_t' {aka 'unsigned int'} [-Wformat=] Cc: Alex Deucher <Alexander.Deucher@amd.com> Cc: kbuild-all@lists.01.org Cc: linux-kernel@vger.kernel.org Reported-by: Nkernel test robot <lkp@intel.com> Fixes: a6c40b17 ("drm/amdgpu: Show IP discovery in sysfs") Signed-off-by: NLuben Tuikov <luben.tuikov@amd.com> Acked-by: NAlex Deucher <Alexander.Deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Prike Liang 提交于
Add 3.1.6 DCE IP and assign relevant sw DM function for the new DCE. Reviewed-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NPrike Liang <Prike.Liang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 17 2月, 2022 9 次提交
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由 Prike Liang 提交于
Needed to properly initialize GC 10.3.7. Signed-off-by: NPrike Liang <Prike.Liang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Prike Liang 提交于
Initialize SDMA engine firmware loading. Signed-off-by: NPrike Liang <Prike.Liang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Prike Liang 提交于
Set smu sw function and enable swSMU support for MP1. Signed-off-by: NPrike Liang <Prike.Liang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Prike Liang 提交于
Set psp sw funcs callback and firmware loading for MP0. Signed-off-by: NPrike Liang <Prike.Liang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Prike Liang 提交于
Set gfxhub function and configure VM for GC block. Signed-off-by: NPrike Liang <Prike.Liang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Prike Liang 提交于
Set nv_common_ip_block for GC 10.3.7. Signed-off-by: NPrike Liang <Prike.Liang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Prike Liang 提交于
Add SMUIO sw function for the new SMUIO block. Signed-off-by: NPrike Liang <Prike.Liang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Prike Liang 提交于
add nbio sw func for the new 7.5.1 nbio block. Signed-off-by: NPrike Liang <Prike.Liang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Luben Tuikov 提交于
Add the "harvest" field to the IP attributes in the IP discovery sysfs visualization, as this field is present in the binary data. At the time of this commit, the harvest data isn't consistently correct in VBIOS, but it is exposed for completeness, in the hopes that VBIOS will be fixed in the future. Cc: Alex Deucher <Alexander.Deucher@amd.com> Signed-off-by: NLuben Tuikov <luben.tuikov@amd.com> Reviewed-by: NChristian König <christian.koenig@amd.com> Reviewed-by: NAlex Deucher <Alexander.Deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 15 2月, 2022 1 次提交
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由 Luben Tuikov 提交于
Add IP discovery data in sysfs. The format is: /sys/class/drm/cardX/device/ip_discovery/die/D/B/I/<attrs> where, X is the card ID, an integer, D is the die ID, an integer, B is the IP HW ID, an integer, aka block type, I is the IP HW ID instance, an integer. <attrs> are the attributes of the block instance. At the moment these include HW ID, instance number, major, minor, revision, number of base addresses, and the base addresses themselves. A symbolic link of the acronym HW ID is also created, under D/, if you prefer to browse by something humanly accessible. Cc: Alex Deucher <Alexander.Deucher@amd.com> Cc: Tom StDenis <tom.stdenis@amd.com> Signed-off-by: NLuben Tuikov <luben.tuikov@amd.com> Reviewed-by: NAlex Deucher <Alexander.Deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 12 2月, 2022 1 次提交
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由 Lang Yu 提交于
Add basic support for GC 10.1.4, it uses same IP blocks with GC 10.1.3 Signed-off-by: NLang Yu <Lang.Yu@amd.com> Reviewed-by: NHuang Rui <ray.huang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 26 1月, 2022 2 次提交
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由 Alex Deucher 提交于
Use the IP versions to set the APU flag when necessary. Reviewed-by: NAaron Liu <aaron.liu@amd.com> Acked-by: NEvan Quan <evan.quan@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Lang Yu 提交于
It doesn't work under IP discovery mode. Make it work! Signed-off-by: NLang Yu <Lang.Yu@amd.com> Reviewed-by: NAlex Deucher <aleander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 19 1月, 2022 3 次提交
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由 Guchun Chen 提交于
This is a following patch to apply the workaround only on those boards with a bad harvest table in ip discovery. Signed-off-by: NGuchun Chen <guchun.chen@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Guchun Chen 提交于
This is a following patch to apply the workaround only on those boards with a bad harvest table in ip discovery. Signed-off-by: NGuchun Chen <guchun.chen@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Guchun Chen 提交于
Early check in amdgpu_discovery_reg_base_init promises this. Signed-off-by: NGuchun Chen <guchun.chen@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 12 1月, 2022 1 次提交
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由 Peng Ju Zhou 提交于
Certain Navy Flounder cards have 2 VCNs, enable it. Signed-off-by: NPeng Ju Zhou <PengJu.Zhou@amd.com> Acked-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NGuchun Chen <guchun.chen@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 30 12月, 2021 1 次提交
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由 Guchun Chen 提交于
A minor typo. Signed-off-by: NGuchun Chen <guchun.chen@amd.com> Reviewed-by: NEvan Quan <evan.quan@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 18 12月, 2021 1 次提交
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由 Alex Deucher 提交于
Used on gfx9 based systems. Fixes incorrect CU counts reported in the kernel log. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1833Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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- 17 12月, 2021 1 次提交
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由 Alex Deucher 提交于
Used on gfx9 based systems. Fixes incorrect CU counts reported in the kernel log. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1833Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 14 12月, 2021 5 次提交
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由 Hawking Zhang 提交于
read and authenticate ip discovery binary getting from vram first, if it is not valid, read and authenticate the one getting from file Signed-off-by: NHawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Hawking Zhang 提交于
To be used to check ip discovery binary signature Signed-off-by: NHawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Hawking Zhang 提交于
add _from_vram in the funciton name to diffrentiate the one used to read from file Signed-off-by: NHawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Hawking Zhang 提交于
To be used when ip_discovery binary is not carried by vbios Signed-off-by: NHawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Leslie Shi 提交于
Guest OS will setup VCN instance 1 which is disabled as an enabled instance and execute initialization work on it, but this causes VCN ib ring test failure on the disabled VCN instance during modprobe: amdgpu 0000:00:08.0: amdgpu: ring vcn_enc_1.0 uses VM inv eng 5 on hub 1 amdgpu 0000:00:08.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on vcn_dec_0 (-110). amdgpu 0000:00:08.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on vcn_enc_0.0 (-110). [drm:amdgpu_device_delayed_init_work_handler [amdgpu]] *ERROR* ib ring test failed (-110). v2: drop amdgpu_discovery_get_vcn_version and rename sriov_config to vcn_config v3: modify VCN's revision in SR-IOV and bare-metal Fixes: baf3f8f3 ("drm/amdgpu: handle SRIOV VCN revision parsing") Signed-off-by: NLeslie Shi <Yuliang.Shi@amd.com> Reviewed-by: NLijo Lazar <lijo.lazar@amd.com> Reviewed-by: NGuchun Chen <guchun.chen@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 03 12月, 2021 1 次提交
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由 Alex Deucher 提交于
For SR-IOV, the IP discovery revision number encodes additional information. Handle that case here. v2: drop additional IP versions Reviewed-by: NGuchun Chen <guchun.chen@amd.com> Acked-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 02 12月, 2021 3 次提交
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由 Guchun Chen 提交于
There is no base reg offset or ip_version set for SDMA2 and SDMA3 on SIENNA_CICHLID, so add them. Signed-off-by: NGuchun Chen <guchun.chen@amd.com> Reviewed-by: NKevin Wang <kevinyang.wang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Jane Jian 提交于
[WHY] for sriov odd# vf will modify vcn0 engine ip revision(due to multimedia bandwidth feature), which will be mismatched with original vcn0 revision [HOW] add new version check for vcn0 disabled revision(3, 0, 192), typically modified under sriov mode Signed-off-by: NJane Jian <Jane.Jian@amd.com> Reviewed-by: NGuchun Chen <guchun.chen@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Guchun Chen 提交于
There is no base reg offset or ip_version set for SDMA2 and SDMA3 on SIENNA_CICHLID, so add them. Signed-off-by: NGuchun Chen <guchun.chen@amd.com> Reviewed-by: NKevin Wang <kevinyang.wang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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