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  1. 05 5月, 2015 1 次提交
  3. 10 4月, 2015 2 次提交
  5. 09 4月, 2015 2 次提交
  7. 08 4月, 2015 1 次提交
  9. 07 4月, 2015 3 次提交
  11. 06 4月, 2015 1 次提交
  13. 05 4月, 2015 2 次提交
  15. 03 4月, 2015 4 次提交
  17. 02 4月, 2015 3 次提交
  19. 01 4月, 2015 5 次提交
  21. 31 3月, 2015 1 次提交
  23. 29 3月, 2015 3 次提交
    • M
      Documentation/ABI:iio:fix typo · 5798cd23
      由 Martin Kepplinger 提交于 
      Signed-off-by: NMartin Kepplinger <martink@posteo.de>
Signed-off-by: NJonathan Cameron <jic23@kernel.org>
      5798cd23
    • O
      iio: add support for hardware fifo · f4f4673b
      由 Octavian Purdila 提交于 
      Some devices have hardware buffers that can store a number of samples
for later consumption. Hardware usually provides interrupts to notify
the processor when the FIFO is full or when it has reached a certain
watermark level. This helps with reducing the number of interrupts to
the host processor and thus it helps decreasing the power consumption.

This patch enables usage of hardware FIFOs for IIO devices in
conjunction with software device buffers. When the hardware FIFO is
enabled the samples are stored in the hardware FIFO. The samples are
later flushed to the device software buffer when the number of entries
in the hardware FIFO reaches the hardware watermark or when a flush
operation is triggered by the user when doing a non-blocking read
on an empty software device buffer.

In order to implement hardware FIFO support the device drivers must
implement the following new operations: setting and getting the
hardware FIFO watermark level, flushing the hardware FIFO to the
software device buffer. The device must also expose information about
the hardware FIFO such it's minimum and maximum watermark and if
necessary a list of supported watermark values. Finally, the device
driver must activate the hardware FIFO when the device buffer is
enabled, if the current device settings allows it.

The software device buffer watermark is passed by the IIO core to the
device driver as a hint for the hardware FIFO watermark. The device
driver can adjust this value to allow for hardware limitations (such
as capping it to the maximum hardware watermark or adjust it to a
value that is supported by the hardware). It can also disable the
hardware watermark (and implicitly the hardware FIFO) it this value is
below the minimum hardware watermark.

Since a driver may support hardware FIFO only when not in triggered
buffer mode (due to different semantics of hardware FIFO sampling and
triggered sampling) this patch changes the IIO core code to allow
falling back to non-triggered buffered mode if no trigger is enabled.
Signed-off-by: NOctavian Purdila <octavian.purdila@intel.com>
Reviewed-by: NLars-Peter Clausen <lars@metafoo.de>
Signed-off-by: NJonathan Cameron <jic23@kernel.org>
      f4f4673b
    • J
      iio: add watermark logic to iio read and poll · 37d34556
      由 Josselin Costanzi 提交于 
      Currently the IIO buffer blocking read only wait until at least one
data element is available.
This patch makes the reader sleep until enough data is collected before
returning to userspace. This should limit the read() calls count when
trying to get data in batches.

Co-author: Yannick Bedhomme <yannick.bedhomme@mobile-devices.fr>
Signed-off-by: NJosselin Costanzi <josselin.costanzi@mobile-devices.fr>
[rebased and remove buffer timeout]
Signed-off-by: NOctavian Purdila <octavian.purdila@intel.com>
Reviewed-by: NLars-Peter Clausen <lars@metafoo.de>
Signed-off-by: NJonathan Cameron <jic23@kernel.org>
      37d34556
  25. 28 3月, 2015 9 次提交
    • H
      iio: Add ABI documentation for in_rot offset value · 8ea06893
      由 Haneen Mohammed 提交于 
      This patch adds ABI documentation entries for in_rot_offset.
At least one user for these is present that is the  HID Sensors Driver.
Signed-off-by: NHaneen Mohammed <hamohammed.sa@gmail.com>
Signed-off-by: NJonathan Cameron <jic23@kernel.org>
      8ea06893
    • D
      iio: Add ABI documentation for illuminance raw and scale values in light · 7cf78db5
      由 Darshana Padmadas 提交于 
      This patchset adds ABI documentation for the following attributes:

in_illuminance_scale, used atleast once in al3320a staging/iio/light/
in_illuminance_calibscale, used atleast once in cm32181
in_illuminance_input, used in cm3232 at least once
in_illuminance_raw used atleast once in al3320a
in_illuminance_clear_raw and in_illuminance_ir_raw exposed by
gp2ap020a00f with modifiers IIO_MOD_LIGHT_CLEAR and
IIO_MOD_LIGHT_IR respectively.
Signed-off-by: NDarshana Padmadas <darshanapadmadas@gmail.com>
Signed-off-by: NJonathan Cameron <jic23@kernel.org>
      7cf78db5
    • L
      iio: st-sensors: add support for lis3lv02d accelerometer · 3acddf74
      由 Linus Walleij 提交于 
      This adds support for the LIS3LV02 accelerometer found in the
ST Microelectronics Nomadik board series.

Cc: devicetree@vger.kernel.org
Cc: Denis CIOCCA <denis.ciocca@st.com>
Acked-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NJonathan Cameron <jic23@kernel.org>
      3acddf74
    • J
      MIPS: KVM: Wire up MSA capability · d952bd07
      由 James Hogan 提交于 
      Now that the code is in place for KVM to support MIPS SIMD Architecutre
(MSA) in MIPS guests, wire up the new KVM_CAP_MIPS_MSA capability.

For backwards compatibility, the capability must be explicitly enabled
in order to detect or make use of MSA from the guest.

The capability is not supported if the hardware supports MSA vector
partitioning, since the extra support cannot be tested yet and it
extends the state that the userland program would have to save.
Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
Acked-by: NPaolo Bonzini <pbonzini@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Gleb Natapov <gleb@kernel.org>
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
Cc: linux-api@vger.kernel.org
Cc: linux-doc@vger.kernel.org
      d952bd07
    • J
      MIPS: KVM: Expose MSA registers · ab86bd60
      由 James Hogan 提交于 
      Add KVM register numbers for the MIPS SIMD Architecture (MSA) registers,
and implement access to them with the KVM_GET_ONE_REG / KVM_SET_ONE_REG
ioctls when the MSA capability is enabled (exposed in a later patch) and
present in the guest according to its Config3.MSAP bit.

The MSA vector registers use the same register numbers as the FPU
registers except with a different size (128bits). Since MSA depends on
Status.FR=1, these registers are inaccessible when Status.FR=0. These
registers are returned as a single native endian 128bit value, rather
than least significant half first with each 64-bit half native endian as
the kernel uses internally.
Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Gleb Natapov <gleb@kernel.org>
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
Cc: linux-api@vger.kernel.org
Cc: linux-doc@vger.kernel.org
      ab86bd60
    • J
      MIPS: KVM: Wire up FPU capability · 5fafd874
      由 James Hogan 提交于 
      Now that the code is in place for KVM to support FPU in MIPS KVM guests,
wire up the new KVM_CAP_MIPS_FPU capability.

For backwards compatibility, the capability must be explicitly enabled
in order to detect or make use of the FPU from the guest.
Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Gleb Natapov <gleb@kernel.org>
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
Cc: linux-api@vger.kernel.org
Cc: linux-doc@vger.kernel.org
      5fafd874
    • J
      MIPS: KVM: Expose FPU registers · 379245cd
      由 James Hogan 提交于 
      Add KVM register numbers for the MIPS FPU registers, and implement
access to them with the KVM_GET_ONE_REG / KVM_SET_ONE_REG ioctls when
the FPU capability is enabled (exposed in a later patch) and present in
the guest according to its Config1.FP bit.

The registers are accessible in the current mode of the guest, with each
sized access showing what the guest would see with an equivalent access,
and like the architecture they may become UNPREDICTABLE if the FR mode
is changed. When FR=0, odd doubles are inaccessible as they do not exist
in that mode.
Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
Acked-by: NPaolo Bonzini <pbonzini@redhat.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Gleb Natapov <gleb@kernel.org>
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
Cc: linux-api@vger.kernel.org
Cc: linux-doc@vger.kernel.org
      379245cd
    • J
      MIPS: KVM: Add Config4/5 and writing of Config registers · c771607a
      由 James Hogan 提交于 
      Add Config4 and Config5 co-processor 0 registers, and add capability to
write the Config1, Config3, Config4, and Config5 registers using the KVM
API.

Only supported bits can be written, to minimise the chances of the guest
being given a configuration from e.g. QEMU that is inconsistent with
that being emulated, and as such the handling is in trap_emul.c as it
may need to be different for VZ. Currently the only modification
permitted is to make Config4 and Config5 exist via the M bits, but other
bits will be added for FPU and MSA support in future patches.

Care should be taken by userland not to change bits without fully
handling the possible extra state that may then exist and which the
guest may begin to use and depend on.
Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Gleb Natapov <gleb@kernel.org>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
      c771607a
    • J
      MIPS: KVM: Implement PRid CP0 register access · 1068eaaf
      由 James Hogan 提交于 
      Implement access to the guest Processor Identification CP0 register
using the KVM_GET_ONE_REG and KVM_SET_ONE_REG ioctls. This allows the
owning process to modify and read back the value that is exposed to the
guest in this register.
Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Gleb Natapov <gleb@kernel.org>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
      1068eaaf
  27. 27 3月, 2015 2 次提交
  29. 26 3月, 2015 1 次提交