提交 · d7071743db31b4f6898b1c742e4b451bb4bc4b02 · openeuler / Kernel

03 10月, 2020 5 次提交

RISC-V: Add EFI stub support. · d7071743

由 Atish Patra 提交于 9月 17, 2020

Add a RISC-V architecture specific stub code that actually copies the
actual kernel image to a valid address and jump to it after boot services
are terminated. Enable UEFI related kernel configs as well for RISC-V.
Signed-off-by: NAtish Patra <atish.patra@wdc.com>
Link: https://lore.kernel.org/r/20200421033336.9663-4-atish.patra@wdc.com
[ardb: - move hartid fetch into check_platform_features()
       - use image_size not reserve_size
       - select ISA_C
       - do not use dram_base]
Signed-off-by: NArd Biesheuvel <ardb@kernel.org>
Signed-off-by: NPalmer Dabbelt <palmerdabbelt@google.com>

d7071743

RISC-V: Add PE/COFF header for EFI stub · cb7d2dd5

由 Atish Patra 提交于 9月 17, 2020

Linux kernel Image can appear as an EFI application With appropriate
PE/COFF header fields in the beginning of the Image header. An EFI
application loader can directly load a Linux kernel Image and an EFI
stub residing in kernel can boot Linux kernel directly.

Add the necessary PE/COFF header.
Signed-off-by: NAtish Patra <atish.patra@wdc.com>
Link: https://lore.kernel.org/r/20200421033336.9663-3-atish.patra@wdc.com
[ardb: - use C prefix for c.li to ensure the expected opcode is emitted
       - align all image sections according to PE/COFF section alignment ]
Signed-off-by: NArd Biesheuvel <ardb@kernel.org>
Reviewed-by: NAnup Patel <anup@brainfault.org>
Signed-off-by: NPalmer Dabbelt <palmerdabbelt@google.com>

cb7d2dd5

RISC-V: Implement late mapping page table allocation functions · e8dcb61f

由 Atish Patra 提交于 9月 17, 2020

Currently, page table setup is done during setup_va_final where fixmap can
be used to create the temporary mappings. The physical frame is allocated
from memblock_alloc_* functions. However, this won't work if page table
mapping needs to be created for a different mm context (i.e. efi mm) at
a later point of time.

Use generic kernel page allocation function & macros for any mapping
after setup_vm_final.
Signed-off-by: NAtish Patra <atish.patra@wdc.com>
Reviewed-by: NAnup Patel <anup@brainfault.org>
Acked-by: NMike Rapoport <rppt@linux.ibm.com>
Signed-off-by: NPalmer Dabbelt <palmerdabbelt@google.com>

e8dcb61f

RISC-V: Add early ioremap support · 6262f661

由 Atish Patra 提交于 9月 17, 2020

UEFI uses early IO or memory mappings for runtime services before
normal ioremap() is usable. Add the necessary fixmap bindings and
pmd mappings for generic ioremap support to work.
Signed-off-by: NAtish Patra <atish.patra@wdc.com>
Reviewed-by: NAnup Patel <anup@brainfault.org>
Reviewed-by: NPalmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: NPalmer Dabbelt <palmerdabbelt@google.com>

6262f661

RISC-V: Move DT mapping outof fixmap · 8f3a2b4a

由 Anup Patel 提交于 9月 17, 2020

Currently, RISC-V reserves 1MB of fixmap memory for device tree. However,
it maps only single PMD (2MB) space for fixmap which leaves only < 1MB space
left for other kernel features such as early ioremap which requires fixmap
as well. The fixmap size can be increased by another 2MB but it brings
additional complexity and changes the virtual memory layout as well.
If we require some additional feature requiring fixmap again, it has to be
moved again.

Technically, DT doesn't need a fixmap as the memory occupied by the DT is
only used during boot. That's why, We map device tree in early page table
using two consecutive PGD mappings at lower addresses (< PAGE_OFFSET).
This frees lot of space in fixmap and also makes maximum supported
device tree size supported as PGDIR_SIZE. Thus, init memory section can be used
for the same purpose as well. This simplifies fixmap implementation.
Signed-off-by: NAnup Patel <anup.patel@wdc.com>
Signed-off-by: NAtish Patra <atish.patra@wdc.com>
Reviewed-by: NPalmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: NPalmer Dabbelt <palmerdabbelt@google.com>

8f3a2b4a

16 9月, 2020 15 次提交

RISC-V: Fix duplicate included thread_info.h · 54701a0d

由 Tian Tao 提交于 9月 14, 2020

asm/thread_info.h is included more than once, Remove the one that isn't
necessary.
Signed-off-by: NTian Tao <tiantao6@hisilicon.com>
Signed-off-by: NPalmer Dabbelt <palmerdabbelt@google.com>

54701a0d

riscv/mm/fault: Set FAULT_FLAG_INSTRUCTION flag in do_page_fault() · a960c132

由 Pekka Enberg 提交于 9月 05, 2020

If the page fault "cause" is EXC_INST_PAGE_FAULT, set the
FAULT_FLAG_INSTRUCTION flag to let handle_mm_fault() and friends know
about it. This has no functional changes because RISC-V uses the default
arch_vma_access_permitted() implementation, which always returns true.
However, dax_pmd_fault(), for example, has a tracepoint that uses
FAULT_FLAG_INSTRUCTION, so we might as well set it.
Signed-off-by: NPekka Enberg <penberg@kernel.org>
Signed-off-by: NPalmer Dabbelt <palmerdabbelt@google.com>

a960c132

riscv/mm/fault: Fix inline placement in vmalloc_fault() declaration · 2baa6d95

由 Pekka Enberg 提交于 9月 05, 2020

The "inline" keyword is in the wrong place in vmalloc_fault()
declaration:

>> arch/riscv/mm/fault.c:56:1: warning: 'inline' is not at beginning of declaration [-Wold-style-declaration]
      56 | static void inline vmalloc_fault(struct pt_regs *regs, int code, unsigned long addr)
         | ^~~~~~

Fix that up.
Reported-by: Nkernel test robot <lkp@intel.com>
Signed-off-by: NPekka Enberg <penberg@kernel.org>
Signed-off-by: NPalmer Dabbelt <palmerdabbelt@google.com>

2baa6d95

riscv: Add cache information in AUX vector · 38f5bd23

由 Zong Li 提交于 8月 31, 2020

There are no standard CSR registers to provide cache information, the
way for RISC-V is to get this information from DT. Currently, AT_L1I_X,
AT_L1D_X and AT_L2_X are present in glibc header, and sysconf syscall
could use them to get information of cache through AUX vector.

The result of 'getconf -a' as follows:
LEVEL1_ICACHE_SIZE                 32768
LEVEL1_ICACHE_ASSOC                8
LEVEL1_ICACHE_LINESIZE             64
LEVEL1_DCACHE_SIZE                 32768
LEVEL1_DCACHE_ASSOC                8
LEVEL1_DCACHE_LINESIZE             64
LEVEL2_CACHE_SIZE                  2097152
LEVEL2_CACHE_ASSOC                 32
LEVEL2_CACHE_LINESIZE              64
Signed-off-by: NZong Li <zong.li@sifive.com>
Reviewed-by: NPalmer Dabbelt <palmerdabbelt@google.com>
Reviewed-by: NPekka Enberg <penberg@kernel.org>
Signed-off-by: NPalmer Dabbelt <palmerdabbelt@google.com>

38f5bd23

riscv: Define AT_VECTOR_SIZE_ARCH for ARCH_DLINFO · b5fca7c5

由 Zong Li 提交于 8月 31, 2020

AT_VECTOR_SIZE_ARCH should be defined with the maximum number of
NEW_AUX_ENT entries that ARCH_DLINFO can contain, but it wasn't defined
for RISC-V at all even though ARCH_DLINFO will contain one NEW_AUX_ENT
for the VDSO address.
Signed-off-by: NZong Li <zong.li@sifive.com>
Reviewed-by: NPalmer Dabbelt <palmerdabbelt@google.com>
Reviewed-by: NPekka Enberg <penberg@kernel.org>
Signed-off-by: NPalmer Dabbelt <palmerdabbelt@google.com>

b5fca7c5

riscv: Set more data to cacheinfo · baf7cbd9

由 Zong Li 提交于 8月 31, 2020

Set cacheinfo.{size,sets,line_size} for each cache node, then we can
get these information from userland through auxiliary vector.
Signed-off-by: NZong Li <zong.li@sifive.com>
Reviewed-by: NPekka Enberg <penberg@kernel.org>
Signed-off-by: NPalmer Dabbelt <palmerdabbelt@google.com>

baf7cbd9

riscv/mm/fault: Move access error check to function · afb8c6fe