1. 19 9月, 2014 2 次提交
    • V
      drm/i915: Limit the watermark to at least 8 entries on gen2/3 · d6feb196
      Ville Syrjälä 提交于
      830 is very unhappy of the watermark value is too low (indicating a very
      high watermark in fact, ie. memory fetch will occur with an almost full
      FIFO). Limit the watermark value to at least 8 cache lines.
      
      That also matches the burst size we use on most platforms. BSpec seems
      to indicate we should limit the watermark to 'burst size + 1'. But on
      gen4 we already use a hardcoded 8 as the watermark value (as the spec
      says we should), so just use 8 as the limit on gen2/3 as well.
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      d6feb196
    • V
      drm/i915: Fix DVO 2x clock enable on 830M · 1c4e0274
      Ville Syrjälä 提交于
      The spec says:
      "For the correct operation of the muxed DVO pins (GDEVSELB/ I2Cdata,
      GIRDBY/I2CClk) and (GFRAMEB/DVI_Data, GTRDYB/DVI_Clk): Bit 31
      (DPLL VCO Enable) and Bit 30 (2X Clock Enable) must be set to “1” in
      both the DPLL A Control Register (06014h-06017h) and DPLL B Control
      Register (06018h-0601Bh)."
      
      The pipe A and B force quirks take care of DPLL_VCO_ENABLE, so we
      just need a bit of special care to handle DPLL_DVO_2X_MODE.
      
      v2: Recompute num_dvo_pipes on the spot, use PIPE_A/PIPE_B instead
          of pipe/!pipe for the register offsets in disable (Daniel)
          Add a comment about the ordering in enable and another one
          about filtering out the DVO 2x bit in state readout
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Tested-by: Thomas Richter <richter@rus.uni-stuttgart.de> (v1)
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      1c4e0274
  2. 17 9月, 2014 9 次提交
  3. 16 9月, 2014 1 次提交
  4. 15 9月, 2014 28 次提交