- 12 11月, 2012 6 次提交
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由 Paulo Zanoni 提交于
When intel_hdmi_detect detects a monitor, set intel_encoder->type with INTEL_OUTPUT_HDMI. Same for DP. This should not break the current code because these variables never change. This will be used after we create the DDI encoder because it will have both DP and HDMI connectors. We won't support eDP+HDMI on the same port, so if an encoder is eDP we should expect it to always remain eDP and never change. Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: NDamien Lespiau <damien.lespiau@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Paulo Zanoni 提交于
Same reason as the previous HDMI commit: the DDI code will have its own encoder init function but still use the DP and HDMI connectors. Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: NDamien Lespiau <damien.lespiau@intel.com> [danvet: kill the unnecessarily added line that Damien spotted in review.] Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Paulo Zanoni 提交于
The goal is to have one single encoder capable of controlling both DP and HDMI outputs. This patch just adds the initial infrastructure, no functional changes. Previously, both intel_dp and intel_hdmi were intel_encoders. Now, these 2 structs do not have intel_encoder as members anymore. The new struct intel_digital_port has intel_encoder as a member, and it also includes intel_dp and intel_hdmi as members. In other words: see the changes inside intel_drv.h: it's the most important change, everything else is only to make it compile and work. For now, each intel_digital_port is still only able to control one of HDMI or DP, but not both together. In the future we should also try to merge the common fields from intel_dp and intel_hdmi (e.g., port). Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: NDamien Lespiau <damien.lespiau@intel.com> [danvet: Add the missing ' ' spotted by Damien Lespiau.] Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Paulo Zanoni 提交于
When we add struct intel_digital_port, there will be no direct way of going from intel_{dp,hdmi} to drm_device: we will need to call container_of(). This patch adds functions to go from intel_{dp,hdmi} to drm_device. The main goal here is to greatly reduce the size of the next patch, where we will change the implementation of the functions we just added here (among other things). Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: NDamien Lespiau <damien.lespiau@gmail.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Paulo Zanoni 提交于
- Replace container_of with enc_to_intel_dp. - Walk through less structures when making assignments. - Rename some variables to keep our naming standards. As a bonus, this will reduce the usage of "struct intel_dp", making the future patch that introduces intel_digital_port smaller and easier to review. Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: NDamien Lespiau <damien.lespiau@gmail.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Daniel Vetter 提交于
The debug message is only relevant on CPT/PPT PCH ports, so move it into the correct if clause. Reviewed-by: NPaulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 27 10月, 2012 3 次提交
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由 Yuly Novikov 提交于
Signed-off-by: NYuly Novikov <ynovikov@chromium.org> [Jani: ripped this change separate from the scaling mode change support] Signed-off-by: NJani Nikula <jani.nikula@intel.com> Reviewed-by: NPaulo Zanoni <paulo.r.zanoni@intel.com> Tested-by: NPaulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Yuly Novikov 提交于
LVDS allowed changing panel fitting scaling mode, while eDP didn't. Copied relevant code from LVDS to eDP. Signed-off-by: NYuly Novikov <ynovikov@chromium.org> [Jani: use fitting mode in intel_panel, remove default mode change] Signed-off-by: NJani Nikula <jani.nikula@intel.com> Reviewed-by: NPaulo Zanoni <paulo.r.zanoni@intel.com> Tested-by: NPaulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Jani Nikula 提交于
At some point the DPCD size was increased, but the debug print not. While at it, switch to using hex dump. Signed-off-by: NJani Nikula <jani.nikula@intel.com> Reviewed-by: NMika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: NPaulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 26 10月, 2012 4 次提交
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由 Paulo Zanoni 提交于
It's an important step :) Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: NRodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Paulo Zanoni 提交于
Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: NRodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Paulo Zanoni 提交于
The cdclk frequency is not always the same, so the value here should be adjusted to match it. Version 2: call intel_ddi_get_cdclk_freq instead of reading CDCLK_FREQ, because the register is just for earlier HW steppings. Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: NRodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Paulo Zanoni 提交于
Same thing as the previous commits. Not renaming this one since it exists since way before Haswell. Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: NDamien Lespiau <damien.lespiau@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 24 10月, 2012 5 次提交
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由 Daniel Vetter 提交于
That thing has grown way too big already. Also move around a comment to the right spot. Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org> Tested-by: NPaulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Daniel Vetter 提交于
Otherwise dp aux won't work on some hsw platforms, since they use a different rawclk than the 125MHz clock used thus far. To absolutely not change anything, round up: That way we get the old 63 divider for the default 125MHz clock. Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org> Tested-by: NPaulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Daniel Vetter 提交于
We need this when the bios forgets even to set that bit up. Most seem to do that, even when they don't set up anything else in the panel power sequencer. Note that on IBX the rawclk is variable according to Bspec, but everyone is using 125MHz. The rawclk is fixed to 125MHz on CPT, but luckily we still have the same register available. On hsw, different variants have different clocks, hence we need to check the register. Since other pieces are driven by the rawclock, too, keep the little helper in a central place. Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org> Tested-by: NPaulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Daniel Vetter 提交于
Like we already do for the LVDS panels. This seems to help greatly in setting up the backlight, since the BIOS might refuse to cooperate. Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org> Tested-by: NPaulo Zanoni <paulo.r.zanoni@intel.com> v2: Move the backlight_off call from panel_off to edp_backlight_off, noticed by Paulo Zanoni. Reviewed-by: NPaulo Zanoni <przanoni@gmail.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Daniel Vetter 提交于
3 changes: - If a given value is unset, use the maximal limits from the eDP spec. - Write back the new values, since otherwise the panel power sequencing hw will not dtrt. - Revert the early bail-out in case the register values are unset. The last change reverts commit bfa3384a Author: Jesse Barnes <jbarnes@virtuousgeek.org> Date: Tue Apr 10 11:58:04 2012 -0700 drm/i915: check PPS regs for sanity when using eDP v2: - Unlock the PP regs as the very first thing. This is a required w/a for cpu eDP on port A, and generally a good idea. - Fixup the panel power control port selection bits. v3: Paulo Zanoni noticed that I've fumbled the computation of the spec limit values. Fix them up. We've also noticed that the t8/t9 values in the vbt/bios-programmed pp are much larger than any limits. My guess is that this is to conceal any backlight enable/disable delays. So by using the much shorter limits from the spec, which only concerns the sink, we risk that we might display before the backlight is fully on, or disable the output while the backlight still has afterglow. I've figured I don't care too much, since this will only happen when both the pp regs are not programmed, and the vbt tables don't contain anything useful. v4: Don't set the port selection bits on hsw/LPT, they don't exist any more. v5: Fixup spelling issues in comments, as noticed by Jesse Barnes. Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org> Tested-by: NPaulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 23 10月, 2012 13 次提交
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由 Daniel Vetter 提交于
... like the comment says. No idea whether this has any effect, but I guess it's better to not lie to the display by acking a test request and never following through with it. This goes back to the commit that originally introduced this code: commit a60f0e38 Author: Jesse Barnes <jbarnes@virtuousgeek.org> Date: Thu Oct 20 15:09:17 2011 -0700 drm/i915: add DP test request handling Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk> Meh'ed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Daniel Vetter 提交于
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Acked-by: NDave Airlie <airlied@gmail.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Daniel Vetter 提交于
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Acked-by: NDave Airlie <airlied@gmail.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Daniel Vetter 提交于
Only really required for dp 1.2. I've hoped this would help with some link training woes I'm fighting, but alas those are only dp 1.1 devices. Also move a comment that went misplaced in the recent refactorings to the right spot again. Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Daniel Vetter 提交于
This requires a few changes since that dpcd value is above the range currently cached by radeon. I've check the dp specs, and above 0xf there's a big gap and nothing that looks like we should cache it while a given device is plugged in. It's also the same value that i915.ko uses. Hence extend the various dpcd arrays in the radeon driver, use proper symbolic constants where applicable (one place overallocated the dpcd array to 25 bytes). Then also drop the rd_interval cache - radeon_dp_link_train_init re-reads the dpcd block, so the values we'll consume in train_cr and train_ce will always be fresh. To avoid needless diff-churn, #define the old size of dpcd as the new one and keep it around. v2: Alex Deucher noticed one place where I've forgotten to replace 8 with DP_RECEIVER_CAP_SIZE. Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Acked-by: NDave Airlie <airlied@gmail.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Daniel Vetter 提交于
Safe for the minor difference that the intel versions get an offset into the link_status as an argument, both are the same again. Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Acked-by: NDave Airlie <airlied@gmail.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Daniel Vetter 提交于
radeon and intel use the exact same definition. Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Acked-by: NDave Airlie <airlied@gmail.com> v2: Kill 2 more helpers in intel_dp.c that I've missed. Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Daniel Vetter 提交于
radeon and intel use the exact same definition. Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Acked-by: NDave Airlie <airlied@gmail.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Jani Nikula 提交于
Move the cached EDID from intel_dp and intel_lvds_connector to intel_connector. Unify cached EDID handling for LVDS and eDP, in preparation for adding more generic EDID caching later. Signed-off-by: NJani Nikula <jani.nikula@intel.com> Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Jani Nikula 提交于
Pave the way for sharing some logic between eDP and LVDS. Based on earlier work by Chris Wilson <chris@chris-wilson.co.uk> CC: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NJani Nikula <jani.nikula@intel.com> Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Jani Nikula 提交于
Create a generic struct intel_panel for sharing a data structure and code between eDP and LVDS panels. Add the new struct to intel_connector so that later on we can have generic EDID and mode reading functions with EDID caching that transparently fallback to fixed mode when EDID is not available. Add intel_panel as a dummy first, and move data (such as the mentioned fixed mode) to it in later patches. Based on earlier work by Chris Wilson <chris@chris-wilson.co.uk> CC: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NJani Nikula <jani.nikula@intel.com> Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk> [danvet: Fixup tiny conflict in intel_dp_destroy.] Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Jani Nikula 提交于
Since we do EDID caching in intel_dp_init, we can do the fixed mode initialization there too. This should not change the functionality apart from initializing fixed mode earlier. Particularly retain the behaviour of only falling back to VBT if EDID is not available to not regress commit 47f0eb22 Author: Keith Packard <keithp@keithp.com> Date: Mon Sep 19 14:33:26 2011 -0700 drm/i915: Only use VBT panel mode on eDP if no EDID is found Signed-off-by: NJani Nikula <jani.nikula@intel.com> Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Jani Nikula 提交于
Get rid of saved int_lvds_connector and int_edp_connector in drm_i915_private. Signed-off-by: NJani Nikula <jani.nikula@intel.com> Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 19 10月, 2012 5 次提交
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由 Paulo Zanoni 提交于
This is the final remaining piece of Haswell DP enablement. After this patch, just calling intel_dp_init on any port will make DP work. We still do not do this because we're currently initializing HDMI on all the ports, so if we replace intel_hdmi_init with intel_dp_init, we will break HDMI, and we can't call both because they share the same registers. Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: NDamien Lespiau <damien.lespiau@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Paulo Zanoni 提交于
Previous patch "drm/i915: add basic Haswell DP link train bits" implemented the basic structure to set the voltage levels and training patterns. This patch adds the higher-level bits that are part of the mode set sequence and hot plug. Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: NDamien Lespiau <damien.lespiau@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Paulo Zanoni 提交于
We have to write the correct values inside intel_dp_set_m_n and then prevent these values from being overwritten later. V2: Unconfuse double negation. Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Paulo Zanoni 提交于
Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: NDamien Lespiau <damien.lespiau@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Paulo Zanoni 提交于
The old rule that the AUX registers are just an offset (+4 and +10) from output_reg is not true anymore, since output_reg in on the CPU and some AUX regs are on the PCH. Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com> [danvet: use the existing #defines as spotted by Damien Lespiau.] Reviewed-by: NDamien Lespiau <damien.lespiau@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 18 10月, 2012 3 次提交
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由 Paulo Zanoni 提交于
Much simpler and looks more like the M/N code inside intel_display.c. Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: NJani Nikula <jani.nikula@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Paulo Zanoni 提交于
Previously, the DP register was used for everything. On Haswell, it was split into DDI_BUF_CTL (which is the new intel_dp->DP register) and DP_TP_CTL. The logic behind this patch is based on a patch written by Shobhit Kumar, but the way the code was written is very different. Credits-to: Shobhit Kumar <shobhit.kumar@intel.com> Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com> [danvet: Fixup the logic error spotted by Jani Nikula.] Reviewed-by: NJani Nikula <jani.nikula@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Paulo Zanoni 提交于
Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: NJani Nikula <jani.nikula@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 12 10月, 2012 1 次提交
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由 Jani Nikula 提交于
Backlight is initialized for eDP, but cleaned up only for eDP on DP-D port. This leaves behind a dangling backlight interface on module unload on machines that have eDP connected to something other than DP-D, and breaks the backlight interface for subsequent module reloads. Fix the cleanup, and thus module reload on affected machines. Reported-by: NImre Deak <imre.deak@intel.com> Signed-off-by: NJani Nikula <jani.nikula@intel.com> Reviewed-by: NMika Kuoppala <mika.kuoppala@intel.com> Tested-by: NImre Deak <imre.deak@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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