1. 26 4月, 2007 5 次提交
  2. 07 4月, 2007 1 次提交
  3. 26 3月, 2007 3 次提交
  4. 03 3月, 2007 1 次提交
  5. 27 2月, 2007 1 次提交
    • M
      [TG3]: TSO workaround fixes. · 7f62ad5d
      Michael Chan 提交于
      1.  Add race condition check after netif_stop_queue().  tg3_tx() runs
          without netif_tx_lock and can race with tg3_start_xmit_dma_bug() ->
          tg3_tso_bug().
      
      2.  Firmware TSO in 5703/5704/5705 also have the same TSO limitation,
          i.e. they cannot handle TSO headers bigger than 80 bytes.  Rename
          TG3_FL2_HW_TSO_1_BUG to TG3_FL2_TSO_BUG and set this flag on
          these chips as well.
      
      3.  Update version to 3.74.
      Signed-off-by: NMichael Chan <mchan@broadcom.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      7f62ad5d
  6. 14 2月, 2007 8 次提交
  7. 09 2月, 2007 1 次提交
    • E
      [TG3]: Avoid an expensive divide. · 6b31a515
      Eric Dumazet 提交于
      During an oprofile session of linux-2.6.20 on a dual opteron system, I noticed
      an expensive divide was done in tg3_poll().
      
      I am using gcc-4.1.1, so the following comment from drivers/net/tg3.c seems
      over-optimistic :
      
      /* Do not place this n-ring entries value into the tp struct itself,
        * we really want to expose these constants to GCC so that modulo et
        * al.  operations are done with shifts and masks instead of with
        * hw multiply/modulo instructions.  Another solution would be to
        * replace things like '% foo' with '& (foo - 1)'.
        */
      #define TG3_RX_RCB_RING_SIZE(tp)        \
               ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
      
      Assembly code before patch :
      (oprofile results included)
         6434  0.0088 :ffffffff803684b9:       mov    0x6f0(%r15),%eax
          587 8.0e-04 :ffffffff803684c0:       and    $0x40000,%eax
         2170  0.0030 :ffffffff803684c5:       cmp    $0x1,%eax
                      :ffffffff803684c8:       lea    0x1(%r13),%eax
                      :ffffffff803684cc:       sbb    %ecx,%ecx
         2051  0.0028 :ffffffff803684ce:       xor    %edx,%edx
                      :ffffffff803684d0:       and    $0x200,%ecx
           20 2.7e-05 :ffffffff803684d6:       add    $0x200,%ecx
         1986  0.0027 :ffffffff803684dc:       div    %ecx
      103427  0.1410 :ffffffff803684de:       cmp    %edx,0xffffffffffffff7c(%rbp)
      
      Assembly code after the suggested patch :
      
      ffffffff803684b9:           mov    0x6f0(%r15),%eax
      ffffffff803684c0:           and    $0x40000,%eax
      ffffffff803684c5:           cmp    $0x1,%eax
      ffffffff803684c8:           sbb    %eax,%eax
      ffffffff803684ca:           inc    %r13d
      ffffffff803684cd:           and    $0x200,%eax
      ffffffff803684d2:           add    $0x1ff,%eax
      ffffffff803684d7:           and    %eax,%r13d
      ffffffff803684da:           cmp    %r13d,0xffffffffffffff7c(%rbp)
      Signed-off-by: NEric Dumazet <dada1@cosmosbay.com>
      Acked-by: NMichael Chan <mchan@broadcom.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      6b31a515
  8. 06 2月, 2007 1 次提交
  9. 09 1月, 2007 1 次提交
  10. 18 12月, 2006 5 次提交
  11. 07 12月, 2006 7 次提交
  12. 22 11月, 2006 2 次提交
  13. 16 11月, 2006 2 次提交
  14. 08 11月, 2006 1 次提交
  15. 06 11月, 2006 1 次提交
    • M
      [TG3]: Fix 2nd ifup failure on 5752M. · 36da4d86
      Michael Chan 提交于
      This fixes a bug reported in:
      
      http://bugzilla.kernel.org/show_bug.cgi?id=7438
      
      tg3_close() turns off the PHY if WoL and ASF are both disabled.  On
      the next tg3_open(), some devices such as the 5752M will not be
      brought up correctly without a PHY reset early in the reset sequence.
      The PHY clock is needed for some internal MAC blocks to function
      correctly.
      
      This problem is fixed by always resetting the PHY early in
      tg3_reset_hw() when it is called from tg3_open() or tg3_resume().
      tg3_setup_phy() can then be called later in the sequence without the
      reset_phy parameter set to 1, since the PHY reset is already done.
      
      Update version to 3.68.
      Signed-off-by: NMichael Chan <mchan@broadcom.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      36da4d86