1. 17 9月, 2015 1 次提交
  2. 25 8月, 2015 4 次提交
  3. 12 8月, 2015 1 次提交
    • H
      clk: track the orphan status of clocks and their children · e6500344
      Heiko Stuebner 提交于
      While children of orphan clocks are not carried in the orphan-list itself,
      they're nevertheless orphans in their own right as they also don't have an
      input-rate available. To ease tracking if a clock is an orphan or has an
      orphan in its parent path introduce an orphan field into struct clk and
      update it and the fields in child-clocks when a clock gets added or removed
      from the orphan-list.
      Suggested-by: NStephen Boyd <sboyd@codeaurora.org>
      Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
      Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
      Cc: Alex Elder <elder@linaro.org>
      Cc: Alexandre Belloni <alexandre.belloni@free-electrons.com>
      Cc: Stephen Warren <swarren@wwwdotorg.org>
      Cc: Max Filippov <jcmvbkbc@gmail.com>
      Cc: kernel@pengutronix.de
      Cc: Zhangfei Gao <zhangfei.gao@linaro.org>
      Cc: Santosh Shilimkar <ssantosh@kernel.org>
      Cc: Chao Xie <chao.xie@marvell.com>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: Stefan Wahren <stefan.wahren@i2se.com>
      Cc: Andrew Bresticker <abrestic@chromium.org>
      Cc: Robert Jarzmik <robert.jarzmik@free.fr>
      Cc: Georgi Djakov <georgi.djakov@linaro.org>
      Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
      Cc: Geert Uytterhoeven <geert+renesas@glider.be>
      Cc: Barry Song <baohua@kernel.org>
      Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
      Cc: Viresh Kumar <viresh.linux@gmail.com>
      Cc: Gabriel FERNANDEZ <gabriel.fernandez@st.com>
      Cc: emilio@elopez.com.ar
      Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
      Cc: Tero Kristo <t-kristo@ti.com>
      Cc: Ulf Hansson <ulf.hansson@linaro.org>
      Cc: Pawel Moll <pawel.moll@arm.com>
      Cc: Michal Simek <michal.simek@xilinx.com>
      [sboyd@codeaurora.org: s/clk/core/ in new function]
      Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
      e6500344
  4. 29 7月, 2015 2 次提交
    • S
      clk: Silence warnings about lock imbalances · a57aa185
      Stephen Boyd 提交于
      The recursive spinlock implementation trips up sparse and it
      complains that these functions have lock imbalances. That isn't
      really true though, so add some __acquires() and __releases()
      information so that sparse is quiet.
      
      drivers/clk/clk.c:116:22: warning: context imbalance in 'clk_enable_lock' - wrong count at exit
      drivers/clk/clk.c:141:9: warning: context imbalance in 'clk_enable_unlock' - unexpected unlock
      Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
      a57aa185
    • S
      clk: Allow providers to configure min/max rates · 9783c0d9
      Stephen Boyd 提交于
      clk providers are using the consumer APIs to set min/max rates on
      the clock they're providing. To encourage clk providers to move
      away from the consumer APIs, add a provider API to set the
      min/max rate of a clock. The assumption is that this is done
      before the clock can be requested via clk_get() and that the
      clock rate is already within the boundaries of the min/max that's
      configured.
      Tested-by: NSudeep Holla <sudeep.holla@arm.com>
      Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
      9783c0d9
  5. 28 7月, 2015 2 次提交
    • B
      clk: fix some determine_rate implementations · 57d866e6
      Boris Brezillon 提交于
      Some determine_rate implementations are not returning an error
      when they failed to adapt the rate according to the rate request.
      Fix them so that they return an error instead of silently
      returning 0.
      Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
      CC: Jonathan Corbet <corbet@lwn.net>
      CC: Tony Lindgren <tony@atomide.com>
      CC: Ralf Baechle <ralf@linux-mips.org>
      CC: "Emilio López" <emilio@elopez.com.ar>
      CC: Maxime Ripard <maxime.ripard@free-electrons.com>
      Cc: Tero Kristo <t-kristo@ti.com>
      CC: Peter De Schrijver <pdeschrijver@nvidia.com>
      CC: Prashant Gaikwad <pgaikwad@nvidia.com>
      CC: Stephen Warren <swarren@wwwdotorg.org>
      CC: Thierry Reding <thierry.reding@gmail.com>
      CC: Alexandre Courbot <gnurou@gmail.com>
      CC: linux-doc@vger.kernel.org
      CC: linux-kernel@vger.kernel.org
      CC: linux-arm-kernel@lists.infradead.org
      CC: linux-omap@vger.kernel.org
      CC: linux-mips@linux-mips.org
      CC: linux-tegra@vger.kernel.org
      Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
      57d866e6
    • B
      clk: change clk_ops' ->determine_rate() prototype · 0817b62c
      Boris Brezillon 提交于
      Clock rates are stored in an unsigned long field, but ->determine_rate()
      (which returns a rounded rate from a requested one) returns a long
      value (errors are reported using negative error codes), which can lead
      to long overflow if the clock rate exceed 2Ghz.
      
      Change ->determine_rate() prototype to return 0 or an error code, and pass
      a pointer to a clk_rate_request structure containing the expected target
      rate and the rate constraints imposed by clk users.
      
      The clk_rate_request structure might be extended in the future to contain
      other kind of constraints like the rounding policy, the maximum clock
      inaccuracy or other things that are not yet supported by the CCF
      (power consumption constraints ?).
      Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
      CC: Jonathan Corbet <corbet@lwn.net>
      CC: Tony Lindgren <tony@atomide.com>
      CC: Ralf Baechle <ralf@linux-mips.org>
      CC: "Emilio López" <emilio@elopez.com.ar>
      CC: Maxime Ripard <maxime.ripard@free-electrons.com>
      Acked-by: NTero Kristo <t-kristo@ti.com>
      CC: Peter De Schrijver <pdeschrijver@nvidia.com>
      CC: Prashant Gaikwad <pgaikwad@nvidia.com>
      CC: Stephen Warren <swarren@wwwdotorg.org>
      CC: Thierry Reding <thierry.reding@gmail.com>
      CC: Alexandre Courbot <gnurou@gmail.com>
      CC: linux-doc@vger.kernel.org
      CC: linux-kernel@vger.kernel.org
      CC: linux-arm-kernel@lists.infradead.org
      CC: linux-omap@vger.kernel.org
      CC: linux-mips@linux-mips.org
      CC: linux-tegra@vger.kernel.org
      [sboyd@codeaurora.org: Fix parent dereference problem in
      __clk_determine_rate()]
      Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
      Tested-by: NRomain Perier <romain.perier@gmail.com>
      Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
      [sboyd@codeaurora.org: Folded in fix from Heiko for fixed-rate
      clocks without parents or a rate determining op]
      Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
      0817b62c
  6. 21 7月, 2015 1 次提交
  7. 08 7月, 2015 2 次提交
  8. 21 6月, 2015 1 次提交
    • B
      clk: add CLK_RECALC_NEW_RATES clock flag for Exynos cpu clock support · d8d91987
      Bartlomiej Zolnierkiewicz 提交于
      This flag is needed to fix the issue with wrong dividers being setup
      by Common Clock Framework when using the new Exynos cpu clock support.
      
      The issue happens because clk_core_set_rate_nolock()  calls
      clk_calc_new_rates(clk, rate) before both pre/post clock notifiers have
      a chance to run.  In case of Exynos cpu clock support pre/post clock
      notifiers are registered for mout_apll clock which is a parent of armclk
      cpu clock and dividers are modified in both pre and post clock notifier.
      This results in wrong dividers values being later programmed by
      clk_change_rate(top).  To workaround the problem CLK_RECALC_NEW_RATES
      flag is added and it is set for mout_apll clock later so the correct
      divider values are re-calculated after both pre and post clock notifiers
      had run.
      
      For example when using "performance" governor on Exynos4210 Origen board
      the cpufreq-dt driver requests to change the frequency from 1000MHz to
      1200MHz and after the change state of the relevant clocks is following:
      
      Without use of CLK_GET_RATE_NOCACHE flag:
      
       fout_apll rate: 1200000000
               fout_apll_div_2 rate: 600000000
                       mout_clkout_cpu rate: 600000000
                               div_clkout_cpu rate: 600000000
                                       clkout_cpu rate: 600000000
               mout_apll rate: 1200000000
                       armclk rate: 1200000000
                       mout_hpm rate: 1200000000
                               div_copy rate: 300000000
                                       div_hpm rate: 300000000
                       mout_core rate: 1200000000
                               div_core rate: 1200000000
                                       div_core2 rate: 1200000000
                                               arm_clk_div_2 rate: 600000000
                                               div_corem0 rate: 300000000
                                               div_corem1 rate: 150000000
                                               div_periph rate: 300000000
                               div_atb rate: 300000000
                                       div_pclk_dbg rate: 150000000
                       sclk_apll rate: 1200000000
                               sclk_apll_div_2 rate: 600000000
      
      With use of CLK_GET_RATE_NOCACHE flag:
      
       fout_apll rate: 1200000000
               fout_apll_div_2 rate: 600000000
                       mout_clkout_cpu rate: 600000000
                               div_clkout_cpu rate: 600000000
                                       clkout_cpu rate: 600000000
               mout_apll rate: 1200000000
                       armclk rate: 1200000000
                       mout_hpm rate: 1200000000
                               div_copy rate: 200000000
                                       div_hpm rate: 200000000
                       mout_core rate: 1200000000
                               div_core rate: 1200000000
                                       div_core2 rate: 1200000000
                                               arm_clk_div_2 rate: 600000000
                                               div_corem0 rate: 300000000
                                               div_corem1 rate: 150000000
                                               div_periph rate: 300000000
                               div_atb rate: 240000000
                                       div_pclk_dbg rate: 120000000
                       sclk_apll rate: 150000000
                               sclk_apll_div_2 rate: 75000000
      
      Without this change cpufreq-dt driver showed ~10 mA larger energy
      consumption when compared to cpufreq-exynos one when "performance"
      cpufreq governor was used on Exynos4210 SoC based Origen board.
      
      This issue was probably meant to be workarounded by use of
      CLK_GET_RATE_NOCACHE and CLK_DIVIDER_READ_ONLY clock flags in
      the original Exynos cpu clock patchset (in "[PATCH v12 6/6] clk:
      samsung: remove unused clock aliases and update clock flags" patch)
      but usage of these flags is not sufficient to fix the issue observed.
      
      Cc: Thomas Abraham <thomas.ab@samsung.com>
      Cc: Tomasz Figa <tomasz.figa@gmail.com>
      Cc: Mike Turquette <mturquette@linaro.org>
      Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
      Signed-off-by: NBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
      Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
      d8d91987
  9. 11 6月, 2015 1 次提交
  10. 06 6月, 2015 1 次提交
  11. 21 5月, 2015 1 次提交
  12. 15 5月, 2015 1 次提交
  13. 13 5月, 2015 1 次提交
  14. 08 5月, 2015 2 次提交
  15. 07 5月, 2015 1 次提交
  16. 02 5月, 2015 1 次提交
  17. 01 5月, 2015 6 次提交
  18. 13 4月, 2015 1 次提交
  19. 13 3月, 2015 6 次提交
  20. 12 3月, 2015 2 次提交
    • M
      clk: introduce clk_is_match · 3d3801ef
      Michael Turquette 提交于
      Some drivers compare struct clk pointers as a means of knowing
      if the two pointers reference the same clock hardware. This behavior is
      dubious (drivers must not dereference struct clk), but did not cause any
      regressions until the per-user struct clk patch was merged. Now the test
      for matching clk's will always fail with per-user struct clk's.
      
      clk_is_match is introduced to fix the regression and prevent drivers
      from comparing the pointers manually.
      
      Fixes: 035a61c3 ("clk: Make clk API return per-user struct clk instances")
      Cc: Russell King <linux@arm.linux.org.uk>
      Cc: Shawn Guo <shawn.guo@linaro.org>
      Cc: Tomeu Vizoso <tomeu.vizoso@collabora.com>
      Signed-off-by: NMichael Turquette <mturquette@linaro.org>
      [arnd@arndb.de: Fix COMMON_CLK=N && HAS_CLK=Y config]
      Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      [sboyd@codeaurora.org: const arguments to clk_is_match() and
      remove unnecessary ternary operation]
      Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
      3d3801ef
    • J
      clk: don't export static symbol · f55ac065
      Julia Lawall 提交于
      The semantic patch that fixes this problem is as follows:
      (http://coccinelle.lip6.fr/)
      
      // <smpl>
      @r@
      type T;
      identifier f;
      @@
      
      static T f (...) { ... }
      
      @@
      identifier r.f;
      declarer name EXPORT_SYMBOL_GPL;
      @@
      
      -EXPORT_SYMBOL_GPL(f);
      // </smpl>
      Signed-off-by: NJulia Lawall <Julia.Lawall@lip6.fr>
      Fixes: 035a61c3 "clk: Make clk API return per-user struct clk instances"
      Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
      f55ac065
  21. 20 2月, 2015 1 次提交
    • T
      clk: Only recalculate the rate if needed · ec02ace8
      Tomeu Vizoso 提交于
      We don't really need to recalculate the effective rate of a clock when a
      per-user clock is removed, if the constraints of the later aren't
      limiting the requested rate.
      
      This was causing problems with clocks that never had a rate set before,
      as rate_req would be zero. Though this could be considered a bug in the
      implementation of those clocks, this should be checked somewhere else.
      
      Fixes: 1c8e6004 ("clk: Add rate constraints to clocks")
      Cc: Thierry Reding <thierry.reding@gmail.com>
      Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
      Signed-off-by: NTomeu Vizoso <tomeu.vizoso@collabora.com>
      Signed-off-by: NMichael Turquette <mturquette@linaro.org>
      ec02ace8
  22. 19 2月, 2015 1 次提交