- 07 6月, 2017 3 次提交
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由 Sascha Hauer 提交于
struct spi_imx_config used to hold data specific to the current transfer. However, other data is in the drivers private data struct. Let's drop struct spi_imx_config and put the variables into the drivers private data struct aswell. Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Sascha Hauer 提交于
__spi_validate makes sure that every transfer has a valid bits_per_word and speed_hz setting. We do not need to fallback to values from the spi_device. Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Sascha Hauer 提交于
When the spi_transfer given in spi_imx_setupxfer is NULL then we have nothing to do. Bail out early in this case so that we do not have to test for t != NULL multiple times later. Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 24 5月, 2017 1 次提交
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由 Sascha Hauer 提交于
This reverts commits 8d4a6cad and 179547e1. Besides the problems already found with this patch it also modifies the spi transfer tx_buf in spi_imx_u32_swap_u8() and spi_imx_u32_swap_u16(). This is hidden from the compiler with an explicit cast from const void* to u32*, so no warning is issued. Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 20 5月, 2017 1 次提交
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由 Jiada Wang 提交于
In case either transfer->tx_buf or transfer->rx_buf is NULL, manipulation of buffer in spi_imx_u32_swap_u[8|16]() will cause NULL pointer dereference crash. Add buffer check at very beginning of spi_imx_u32_swap_u[8|16](), to avoid such crash. Signed-off-by: NJiada Wang <jiada_wang@mentor.com> Reported-by: NLeonard Crestez <leonard.crestez@nxp.com> Tested-by: NLeonard Crestez <leonard.crestez@nxp.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 14 5月, 2017 1 次提交
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由 Jiada Wang 提交于
previously burst length (BURST_LENGTH) is always set to equal to bits_per_word, causes a 10us gap between each word in transfer, which significantly affects performance. This patch uses 32 bits transfer to simulate lower bits transfer, and adjusts burst length runtimely to use biggeest burst length as possible to reduce the gaps in transfer for PIO mode. Signed-off-by: NJiada Wang <jiada_wang@mentor.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 26 4月, 2017 1 次提交
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由 Moritz Fischer 提交于
This adds support for using GPIOs for chipselects as described by the default dt-bindings. Signed-off-by: NMoritz Fischer <mdf@kernel.org> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 25 4月, 2017 2 次提交
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由 Leif Middelschulte 提交于
This patch implements consideration of the SPI_READY mode flag as defined in spi.h. It extends the device tree bindings to support the values defined by the reference manual for the DRCTL field. Thus supporting edge-triggered and level-triggered bursts. Signed-off-by: NLeif Middelschulte <Leif.Middelschulte@gmail.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Colin Ian King 提交于
trivial fix to spelling mistake in dbg_err messages Signed-off-by: NColin Ian King <colin.king@canonical.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 22 4月, 2017 2 次提交
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由 Vignesh R 提交于
Flash filesystems like JFFS2, UBIFS and MTD block layer can provide vmalloc'd or kmap'd buffers that cannot be mapped using dma_map_sg() and can potentially be in memory region above 32bit addressable region(ie buffers belonging to memory region backed by LPAE) of DMA, implement spi_flash_can_dma() interface to inform SPI core not to map such buffers. When buffers are not mapped for DMA, then use a pre allocated bounce buffer(64K = typical flash erase sector size) to read from flash and then do a copy to actual destination buffer. This is approach is much faster than using memcpy using CPU and also reduces CPU load. With this patch, UBIFS read speed is ~18MB/s and CPU utilization <20% on DRA74 Rev H EVM. Performance degradation is negligible when compared with non bounce buffer case while using UBIFS. Signed-off-by: NVignesh R <vigneshr@ti.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Vignesh R 提交于
Add an interface analogous to ->can_dma() for spi_flash_read() interface. This will enable SPI controller drivers to inform SPI core when not to do DMA mappings. Signed-off-by: NVignesh R <vigneshr@ti.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 19 4月, 2017 3 次提交
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由 Marek Vasut 提交于
The dw_mmio driver disables the block clock before unregistering the host. The code unregistering the host may access the SPI block registers. If register access happens with block clock disabled, this may lead to a bus hang. Disable the clock after unregistering the host to prevent such situation. This bug was observed on Altera Cyclone V SoC. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Mark Brown <broonie@kernel.org> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Hauke Mehrtens 提交于
The generic SPI code calculates how long the issued transfer would take and adds 100ms in addition to the timeout as tolerance. On my 500 MHz Lantiq Mips SoC I am getting timeouts from the SPI like this when the system boots up: m25p80 spi32766.4: SPI transfer timed out blk_update_request: I/O error, dev mtdblock3, sector 2 SQUASHFS error: squashfs_read_data failed to read block 0x6e After increasing the tolerance for the timeout to 200ms I haven't seen these SPI transfer time outs any more. The Lantiq SPI driver in use here has an extra work queue in between, which gets triggered when the controller send the last word and the hardware FIFOs used for reading and writing are only 8 words long. Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Quentin Schulz 提交于
This adds deepest (Backup+Self-Refresh) PM support to the ATMEL SAMA5D2 SoC's SPI controller. When resuming from deepest state, it is required to restore MR register as the registers are lost since VDD core has been shut down when entering deepest state on the SAMA5D2. Signed-off-by: NQuentin Schulz <quentin.schulz@free-electrons.com> Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: NNicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 12 4月, 2017 1 次提交
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由 Quentin Schulz 提交于
The SPI controller configuration during the init can be reused, for the resume function for example. Let's move this configuration to a separate function. Signed-off-by: NQuentin Schulz <quentin.schulz@free-electrons.com> Acked-by: NNicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 08 4月, 2017 1 次提交
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由 Bastian Stender 提交于
The orion spi driver currently only supports the normal (i.e. MSB) mode. This patch adds LSB first mode. Also correct the comment about supported SPI modes that was left over by b15d5d70 ("spi/orion: Add SPI_CHPA and SPI_CPOL support to kirkwood driver."). Signed-off-by: NBastian Stender <bst@pengutronix.de> Acked-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 06 4月, 2017 1 次提交
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由 Rabin Vincent 提交于
The num-cs property is a required property according to the binding documentation. However, if it is not present, the driver currently simply uses random junk from the stack for the num-cs since the variable whose pointer is passed to of_property_read_u32() is not initialized. Signed-off-by: NRabin Vincent <rabinv@axis.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 30 3月, 2017 1 次提交
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由 Colin Ian King 提交于
trivial fix to spelling mistake in dev_err error message Signed-off-by: NColin Ian King <colin.king@canonical.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 27 3月, 2017 1 次提交
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由 Vignesh R 提交于
commit 1351aaeb ("spi: spi-ti-qspi: Use dma_engine wrapper for dma memcpy call") introduced this warning: drivers/spi/spi-ti-qspi.c: In function 'ti_qspi_dma_xfer': drivers/spi/spi-ti-qspi.c:398:21: warning: unused variable 'dma_dev' [-Wunused-variable] struct dma_device *dma_dev = chan->device; Fix it by removing the unused variable. Signed-off-by: NVignesh R <vigneshr@ti.com> Reported-by: NStephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 25 3月, 2017 2 次提交
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由 Akinobu Mita 提交于
When running the spi-loopback-test with slower clock rate like 10 KHz, the test for 251 bytes transfer was failed. This failure triggered an spi-omap2-mcspi's error message "DMA RX last word empty". This message means that PIO for reading the remaining bytes due to the DMA transfer length reduction is failed. This problem can be fixed by polling OMAP2_MCSPI_CHSTAT_RXS bit in channel status register to wait until the receive buffer register is filled. Cc: Mark Brown <broonie@kernel.org> Signed-off-by: NAkinobu Mita <akinobu.mita@gmail.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Vignesh R 提交于
Instead of calling device_prep_dma_memcpy() directly with dma_device pointer, use the newly introduced dmaengine_prep_dma_memcpy() wrapper API. Signed-off-by: NVignesh R <vigneshr@ti.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 21 3月, 2017 1 次提交
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由 Colin Ian King 提交于
A multiplication of 8U * xfer-len with the type of a 32 bit unsigned int is evaluated using 32 bit arithmetic and then used in a context that expects an expression of type unsigned long long (64 bits). Avoid any potential overflow by casting BITS_PER_BYTE to unsigned long long. Detected by CoverityScan, CID#1419691 ("Unintentional integer overflow") Fixes: ea9936f3 ("spi: loopback-test: add elapsed time check") Signed-off-by: NColin Ian King <colin.king@canonical.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 20 3月, 2017 1 次提交
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由 Icenowy Zheng 提交于
The spi-sun6i driver have already got the ability to do large transfers. However, the max transfer size reported is still fifo depth - 1. Update the max transfer size reported to the max value possible. Reported-by: NMartin Ayotte <martinayotte@gmail.com> Signed-off-by: NIcenowy Zheng <icenowy@aosc.xyz> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 18 3月, 2017 7 次提交
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由 Frode Isaksen 提交于
Add explanation about using the the rx buffer as the dummy tx buffer. Signed-off-by: NFrode Isaksen <fisaksen@baylibre.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Akinobu Mita 提交于
This adds a new test to check whether the spi_transfer.delay_usecs setting has properly taken effect. Signed-off-by: NAkinobu Mita <akinobu.mita@gmail.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Akinobu Mita 提交于
This adds checks whether the elapsed time is longer than the minimam estimated time. The estimated time is calculated with the total transfer length per clock rate and optional spi_transfer.delay_usecs. Signed-off-by: NAkinobu Mita <akinobu.mita@gmail.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Akinobu Mita 提交于
In order to test various spi_messages including zero-length transfer, this adds zero length into the iterate_len list. Signed-off-by: NAkinobu Mita <akinobu.mita@gmail.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Akinobu Mita 提交于
The spi-loopback-test module currently cannot test the spi_message including a zero-length transfer. Because the zero-length transfer is treated as a special value in several meanings. 1. The number of spi_transfer to execute in one test case is described by spi_test.transfer_count. It is normally computed by counting number of transfers with len > 0 in spi_test.transfers array. This change stops the detection for the number of spi_transfer. Each spi_test.transfer_count needs to be filled by hand now. 2. The spi_test.iterate_len is a list of transfer length to iterate on. This list is terminated by zero, so zero-length transfer cannot be included. This changes the terminal value from 0 to -1. 3. The length for the spi_transfer masked by spi_test.iterate_transfer_mask is iterated. Before starting the iteration, the default value which is statically initialized is applied. In order to specify the default value, zero-length is reserved. Currently, the default values are always '1'. So this removes this trick and add '1' to iterate_len list. By applying all these changes, the spi-loopback-test can execute spi messages with zero-length transfer. Signed-off-by: NAkinobu Mita <akinobu.mita@gmail.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Akinobu Mita 提交于
When the loopback parameter is set, rx_buf are compared with tx_buf after the spi_message is executed. But the first byte of buffer is not checked. Signed-off-by: NAkinobu Mita <akinobu.mita@gmail.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Akinobu Mita 提交于
The test "two tx-transfers - alter first" actually alters the second not the first transfer. Similarly the test "two tx-transfers - alter second" actually alters the first not the second transfer. The mismatches for the two symmetrical tests cancel each other's mistakes. But it's better to fix the mismatches to avoid confusion. Signed-off-by: NAkinobu Mita <akinobu.mita@gmail.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 17 3月, 2017 1 次提交
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由 Frode Isaksen 提交于
Fix compile error caused by missing vmalloc() definition on x86 (and maybe other platforms) by including vmalloc.h. Signed-off-by: NFrode Isaksen <fisaksen@baylibre.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 16 3月, 2017 5 次提交
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由 Ben Whitten 提交于
Add entry for the semtech sx1301 baseband processor implementing a LoRa concentrator IP. At this time this chip requires an spidev userspace driver. Signed-off-by: NBen Whitten <ben.whitten@lairdtech.com> Signed-off-by: NSteve deRosier <derosier@gmail.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Frode Isaksen 提交于
Using vmalloc'ed buffers will use one SG entry for each page, that may provoke DMA errors for large transfers. Also vmalloc'ed buffers may cause errors on CPU's with VIVT cache. Add this option to catch these errors when testing. Note that to catch VIVT cache errors, checking the rx range has to be disabled, so this option has been added as well. Signed-off-by: NFrode Isaksen <fisaksen@baylibre.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Frode Isaksen 提交于
Using vmalloc'ed buffers will fail since daVinci has VIVT cache and only the kernel lowmem virtual address is invalidated/flushed when performing DMA. The virtual address returned from vmalloc() is not invalidated/flushed and may contain stale data when returning from spi_sync(). Fixes errors when running UBIFS over SPI NOR. Revert this when all upper layer users of vmalloc'ed buffers sent to SPI handles cache flushing/invalidating. Signed-off-by: NFrode Isaksen <fisaksen@baylibre.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Frode Isaksen 提交于
Higher bitrate and lower CPU load if using PIO in this case. Signed-off-by: NFrode Isaksen <fisaksen@baylibre.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Frode Isaksen 提交于
When doing rx-only transfer, the transfer will fail if the number of SG entries exceeds 20. This happens because the eDMA DMA engine is limited to 20 SG entries in one transaction, and when the DMA transcation is resumed (which takes > 150us), rx errors occurs because the slave is still transmitting. Fix this by using the rx buffer as the dummy tx buffer, so that resuming the rx transcation happens at the same time as resuming the tx transcation. Signed-off-by: NFrode Isaksen <fisaksen@baylibre.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 14 3月, 2017 2 次提交
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由 Jayachandran C 提交于
ARCH_VULCAN arm64 platform (for Broadcom Vulcan ARM64 processors) has been discontinued. Cavium's ThunderX2 CN99XX (ARCH_THUNDER2) will be the next revision of the platform. Update compile dependencies and ACPI ID to reflect this change. There is not need to retain ARCH_VULCAN since the Vulcan processor was never in production and ARCH_VULCAN will be deleted soon. Signed-off-by: NJayachandran C <jnair@caviumnetworks.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Liu Xiang 提交于
Irq_dispose_mapping should be called in err path to release the resources that irq_of_parse_and_map requested. Signed-off-by: NLiu Xiang <liu.xiang6@zte.com.cn> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 13 3月, 2017 2 次提交
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由 Jonas Gorski 提交于
Add required binding support to probe through device tree. Signed-off-by: NJonas Gorski <jonas.gorski@gmail.com> Acked-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Jonas Gorski 提交于
The HSSPI block actually has two clock inputs, one for gating the block, and one for the PLL rate. To allow these to be represented as two clocks, add support for retrieving the rate from a separate "pll" clock, if the "hsspi" clock does not provide one. Signed-off-by: NJonas Gorski <jonas.gorski@gmail.com> Acked-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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