- 08 10月, 2018 37 次提交
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由 Aapo Vienamo 提交于
Add quirk to disable the card clock during configuration of the tap value in tegra_sdhci_set_tap() and issue sdhci_reset() after value change. This is a workaround to avoid propagation of a potential glitch caused by setting the tap value. Signed-off-by: NAapo Vienamo <avienamo@nvidia.com> Acked-by: NThierry Reding <treding@nvidia.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Aapo Vienamo 提交于
Set NVQUIRK_HAS_PADCALIB on Tegra210 and Tegra186 to enable automatic pad drive strength calibration. Signed-off-by: NAapo Vienamo <avienamo@nvidia.com> Acked-by: NThierry Reding <treding@nvidia.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Aapo Vienamo 提交于
Run the automatic pad calibration after voltage switching if tegra_host->pad_calib_required is set. Signed-off-by: NAapo Vienamo <avienamo@nvidia.com> Acked-by: NThierry Reding <treding@nvidia.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Aapo Vienamo 提交于
Parse the pad drive strength calibration offsets from the device tree. Program the calibration offsets in accordance with the current signaling mode. Signed-off-by: NAapo Vienamo <avienamo@nvidia.com> Acked-by: NThierry Reding <treding@nvidia.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Aapo Vienamo 提交于
Disable the card clock during automatic pad drive strength calibration and re-enable it afterwards. Signed-off-by: NAapo Vienamo <avienamo@nvidia.com> Acked-by: NThierry Reding <treding@nvidia.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Aapo Vienamo 提交于
Automatic pad drive strength calibration is performed on a separate pad identical to the ones used for driving the actual bus. Power on the calibration pad during the calibration procedure and power it off afterwards to save power. Signed-off-by: NAapo Vienamo <avienamo@nvidia.com> Reviewed-by: NMikko Perttunen <mperttunen@nvidia.com> Acked-by: NThierry Reding <treding@nvidia.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Aapo Vienamo 提交于
Configure the voltage reference used by the automatic pad drive strength calibration procedure. The value is a magic number from the TRM. Signed-off-by: NAapo Vienamo <avienamo@nvidia.com> Acked-by: NThierry Reding <treding@nvidia.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Aapo Vienamo 提交于
Implement polling with 10 ms timeout for automatic pad drive strength calibration. Signed-off-by: NAapo Vienamo <avienamo@nvidia.com> Acked-by: NThierry Reding <treding@nvidia.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Aapo Vienamo 提交于
Parse the pinctrl state and nvidia,only-1-8-v properties from the device tree. Validate the pinctrl and regulator configuration before unmasking UHS modes. Implement pad voltage state reconfiguration in the mmc start_signal_voltage_switch() callback. Add NVQUIRK_NEEDS_PAD_CONTROL and add set it for Tegra210 and Tegra186. The pad configuration is done in the mmc callback because the order of pad reconfiguration and sdhci voltage switch depend on the voltage to which the transition occurs. Signed-off-by: NAapo Vienamo <avienamo@nvidia.com> Acked-by: NThierry Reding <treding@nvidia.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Wolfram Sang 提交于
This variable is unused now after some refactoring. Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Wolfram Sang 提交于
Concise, but still readable. Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Masaharu Hayakawa 提交于
SDR104, HS200 and HS400 need to check for SCC error. If SCC error is detected, retuning is necessary. Signed-off-by: NMasaharu Hayakawa <masaharu.hayakawa.ry@renesas.com> [Niklas: update commit message] Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Masaharu Hayakawa 提交于
Checking for SCC error during retuning is unnecessary. Signed-off-by: NMasaharu Hayakawa <masaharu.hayakawa.ry@renesas.com> [Niklas: fix small style issue] Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Masahiro Yamada 提交于
for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) clock <<= 1; ... is too tricky, hence I replaced with roundup_pow_of_two(divisor) >> 2 '(clk >> 22) & 0x1' is the bit test for the 1/1 divisor, but it is not clear. 'divisor <= 1' is easier to understand. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Masahiro Yamada 提交于
renesas_sdhi_clk_start() and renesas_sdhi_clk_stop() are now only called from renesas_sdhi_set_clock(). Merge them. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Jisheng Zhang 提交于
When using DMA, if the DMA addr spans 128MB boundary, we have to split the DMA transfer into two so that each one doesn't exceed the boundary. Signed-off-by: NJisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Jisheng Zhang 提交于
Add this hook so that it can be overridden with driver specific implementations. We also let the original sdhci_adma_write_desc() accept &desc so that the function can set its new value. Then export the function so that it could be reused by driver's specific implementations. Signed-off-by: NJisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Jisheng Zhang 提交于
This patch adds adma_table_cnt member to struct sdhci_host to give more flexibility to drivers to control the ADMA table count. Default value of adma_table_cnt is set to (SDHCI_MAX_SEGS * 2 + 1). Signed-off-by: NJisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Rob Herring 提交于
In preparation to remove the node name pointer from struct device_node, convert printf users to use the %pOFn format specifier. Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Hu Ziji <huziji@marvell.com> Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: linux-mmc@vger.kernel.org Signed-off-by: NRob Herring <robh@kernel.org> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Aapo Vienamo 提交于
Allow SDHCI drivers to hook code before and after sdhci_request() by making it externally visible. Signed-off-by: NAapo Vienamo <avienamo@nvidia.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Wang Dongsheng 提交于
After host requests RESET_FOR_ALL action, the hardware output an interrupt for OS and waiting for the OS to approve. Before writing this fix, ACPI GED has handled the interrupt. But the ACPI GED belongs to a slow process, and sometimes the handling process time is more than 100ms(Mutex wait more than 100ms). So drop the GED solution and add this quirk fix. Signed-off-by: NWang Dongsheng <dongsheng.wang@hxt-semitech.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Wang Dongsheng 提交于
The device specific resource can be free in free_slot after removing host controller. Signed-off-by: NWang Dongsheng <dongsheng.wang@hxt-semitech.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Yinbo Zhu 提交于
In tuning mode of operation, when TBCTL[TB_EN] is set, eSDHC may report one of the following errors : 1)Tuning error while running tuning operation where SYSCTL2[SAMPCLKSEL] will not get set even when SYSCTL2[EXTN] is reset. OR 2)Data transaction error (e.g. IRQSTAT[DCE], IRQSTAT[DEBE]) during data transaction errors. This issue occurs when the data window sampled within eSDHC is in full cycle. So, in that case, eSDHC is not able to find out the start and end points of the data window and sets the sampling pointer at default location (which is middle of the internal SD clock). If this sampling point coincides with the data eye boundary, then it can result in the above mentioned errors. Impact: Tuning mode of operation for SDR50, SDR104 or HS200 speed modes may not work properly Workaround: In case eSDHC reports tuning error or data errors in tuning mode of operation, by add the erratum A008171 support to fix the issue. Signed-off-by: NYinbo Zhu <yinbo.zhu@nxp.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Yinbo Zhu 提交于
This patch is to add tuning error codes to judge tuning state Signed-off-by: NYinbo Zhu <yinbo.zhu@nxp.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Masahiro Yamada 提交于
Here is another TMIO MMC variant found in Socionext UniPhier SoCs. As commit b6147490 ("mmc: tmio: split core functionality, DMA and MFD glue") said, these MMC controllers use the IP from Panasonic. However, the MMC controller in the TMIO (Toshiba Mobile IO) MFD chip was the first upstreamed user of this IP. The common driver code for this IP is now called 'tmio-mmc-core' in Linux although it is a historical misnomer. Anyway, this driver select's MMC_TMIO_CORE to borrow the common code from tmio-mmc-core.c Older UniPhier SoCs (LD4, Pro4, sLD8) support the external DMA engine like renesas_sdhi_sys_dmac.c. The difference is UniPhier SoCs use a single DMA channel whereas Renesas chips request separate channels for RX and TX. Newer UniPhier SoCs (Pro5 and later) support the internal DMA engine like renesas_sdhi_internal_dmac.c The register map is almost the same, so I guess Renesas and Socionext use the same internal DMA hardware. The main difference is, the register offsets are doubled for Renesas. Renesas Socionext SDHI UniPhier DM_CM_DTRAN_MODE 0x820 0x410 DM_CM_DTRAN_CTRL 0x828 0x414 DM_CM_RST 0x830 0x418 DM_CM_INFO1 0x840 0x420 DM_CM_INFO1_MASK 0x848 0x424 DM_CM_INFO2 0x850 0x428 DM_CM_INFO2_MASK 0x858 0x42c DM_DTRAN_ADDR 0x880 0x440 DM_DTRAN_ADDREX --- 0x444 This comes from the difference of host->bus_shift; 2 for Renesas SoCs, and 1 for UniPhier SoCs. Also, the datasheet for UniPhier SoCs defines DM_DTRAN_ADDR and DM_DTRAN_ADDREX as two separate registers. It could be possible to factor out the DMA common code by introducing some hooks to cope with platform quirks, but this patch does not touch that for now. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Acked-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Masahiro Yamada 提交于
tmio_mmc_set_clock() is full of quirks because different SoC vendors extended this in different ways. The original IP defines the divisor range 1/2 ... 1/512. bit 7 is set: 1/512 bit 6 is set: 1/256 ... bit 0 is set: 1/4 all bits clear: 1/2 It is platform-dependent how to achieve the 1/1 clock. I guess the TMIO-MFD variant uses the clock selector outside of this IP, as far as I see tmio_core_mmc_clk_div() in drivers/mfd/tmio_core.c I guess bit[7:0]=0xff is Renesas-specific extension. Socionext (and Panasonic) uses bit 10 (CLKSEL) for 1/1. Also, newer versions of UniPhier SoC variants use bit 16 for 1/1024. host->clk_update() is only used by the Renesas variants, whereas host->set_clk_div() is only used by the TMIO-MFD variants. To cope with this mess, promote tmio_mmc_set_clock() to a new platform hook ->set_clock(), and melt the old two hooks into it. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Masahiro Yamada 提交于
tmio_mmc_clk_stop(host) is equivalent to tmio_mmc_set_clock(host, 0). This replacement is needed for the next commit. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Paul Cercueil 提交于
The JZ4725B is the first JZ SoC version that introduced a 32-bit IMASK register, not the JZ4750. Signed-off-by: NPaul Cercueil <paul@crapouillou.net> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Wolfram Sang 提交于
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: NSimon Horman <horms+renesas@verge.net.au> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Sergei Shtylyov 提交于
I've successfully tested eMMC on the V3H Starter Kit board and since the R8A77970 SoC has a single SDHI core, it can't be a subject to the known RX DMA errata. Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org> Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Sergei Shtylyov 提交于
Remove the stray underscore in the DM_CM_DTRAN_MODE.BUS_WIDTH register field name and fix the typo in the comment of the #define DTRAN_MODE_CH_NUM_CH1. Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: NSimon Horman <horms+renesas@verge.net.au> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Paul Cercueil 提交于
Depending on MACH_JZ4740 | MACH_JZ4780 prevent us from creating a generic kernel that works on more than one MIPS board. Instead, we just depend on MIPS being set. Signed-off-by: NPaul Cercueil <paul@crapouillou.net> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Igor Opaniuk 提交于
Enable access to the RPMB on the on-board eMMC of the Poplar board. Signed-off-by: NIgor Opaniuk <igor.opaniuk@linaro.org> Acked-by: NShawn Guo <shawn.guo@linaro.org> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Fabrizio Castro 提交于
We need r8a774a1 to be whitelisted for SDHI to work on the RZ/G2M, but we don't care about the revision of the SoC, so just whitelist the generic part number. Signed-off-by: NFabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: NBiju Das <biju.das@bp.renesas.com> Reviewed-by: NSimon Horman <horms+renesas@verge.net.au> Reviewed-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Michal Simek 提交于
When mmc-pwrseq property is passed mmc_pwrseq_alloc() can return -EPROBE_DEFER because driver for power sequence provider is not probed yet. Do not show error message when this situation happens. Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Srinath Mannam 提交于
Add ACPI support to all IPROC SDHCI variants. Signed-off-by: NSrinath Mannam <srinath.mannam@broadcom.com> Reviewed-by: NRay Jui <ray.jui@broadcom.com> Reviewed-by: NScott Branden <scott.branden@broadcom.com> Reviewed-by: NVladimir Olovyannikov <vladimir.olovyannikov@broadcom.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Adrian Hunter 提交于
Convert DT properties to generic device properties so that drivers can get properties from DT or ACPI. Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com> Tested-by: NSrinath Mannam <srinath.mannam@broadcom.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 06 10月, 2018 3 次提交
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由 Maxime Chevallier 提交于
When offloading the L3 and L4 csum computation on TX, we need to extract the l3_proto from the ethtype, independently of the presence of a vlan tag. The actual driver uses skb->protocol as-is, resulting in packets with the wrong L4 checksum being sent when there's a vlan tag in the packet header and checksum offloading is enabled. This commit makes use of vlan_protocol_get() to get the correct ethtype regardless the presence of a vlan tag. Fixes: 3f518509 ("ethernet: Add new driver for Marvell Armada 375 network unit") Signed-off-by: NMaxime Chevallier <maxime.chevallier@bootlin.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Wenwen Wang 提交于
In yam_ioctl(), the concrete ioctl command is firstly copied from the user-space buffer 'ifr->ifr_data' to 'ioctl_cmd' and checked through the following switch statement. If the command is not as expected, an error code EINVAL is returned. In the following execution the buffer 'ifr->ifr_data' is copied again in the cases of the switch statement to specific data structures according to what kind of ioctl command is requested. However, after the second copy, no re-check is enforced on the newly-copied command. Given that the buffer 'ifr->ifr_data' is in the user space, a malicious user can race to change the command between the two copies. This way, the attacker can inject inconsistent data and cause undefined behavior. This patch adds a re-check in each case of the switch statement if there is a second copy in that case, to re-check whether the command obtained in the second copy is the same as the one in the first copy. If not, an error code EINVAL will be returned. Signed-off-by: NWenwen Wang <wang6495@umn.edu> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Wenwen Wang 提交于
In cxgb_extension_ioctl(), the command of the ioctl is firstly copied from the user-space buffer 'useraddr' to 'cmd' and checked through the switch statement. If the command is not as expected, an error code EOPNOTSUPP is returned. In the following execution, i.e., the cases of the switch statement, the whole buffer of 'useraddr' is copied again to a specific data structure, according to what kind of command is requested. However, after the second copy, there is no re-check on the newly-copied command. Given that the buffer 'useraddr' is in the user space, a malicious user can race to change the command between the two copies. By doing so, the attacker can supply malicious data to the kernel and cause undefined behavior. This patch adds a re-check in each case of the switch statement if there is a second copy in that case, to re-check whether the command obtained in the second copy is the same as the one in the first copy. If not, an error code EINVAL is returned. Signed-off-by: NWenwen Wang <wang6495@umn.edu> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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