Avoton/Rangeley are based on Silvermount micro-architecture, like
Bay Trail, and uses the INTEL_SPI_BYT method to drive SPI.

Cc: stable@vger.kernel.org
Signed-off-by: NJoakim Tjernlund <joakim.tjernlund@infinera.com>
Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

At least on Lenovo Thinkpad Yoga, the BIOS seems to monitor the SPI-NOR
write protection bit and if it is flipped to read/write it assumes the
BIOS configuration was changed on next reboot. It then, for unknown
reasons, resets the BIOS settings back to default.

We can prevent this by just leaving the write protection bit intact and
let the SPI-NOR driver know whether the device is writable or not. In
case of this particular Lenovo the SPI-NOR flash will be exposed as
read-only.

Fixes: ff00d7a3 ("mfd: lpc_ich: Add support for SPI serial flash host controller")
Link: https://bugzilla.kernel.org/show_bug.cgi?id=195951Reported-by: NAbdó Roig-Marange <abdo.roig@gmail.com>
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Like Intel Apollo Lake, Gemini Lake exposes the serial SPI flash device BAR
through hidden P2SB PCI device. We use the same mechanism than Apollo Lake
to read the BAR and pass it to the driver.
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

This patches adds the first minimal support to the upstream Linux tree.
Signed-off-by: NPriyalee Kushwaha <priyalee.kushwaha@intel.com>
Signed-off-by: NAlan Cox <alan@linux.intel.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Assign iTCO_version which effectively enables watchdog device on
Intel Apollo Lake PCH.
Signed-off-by: NTan Jui Nee <jui.nee.tan@intel.com>
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

First of all, remove stalled references to datasheets. If someone knows
the document numbers, it would be added later.

Second, remove FSF snail address since it's subject to change. Actual
information can be found on FSF site on the internet.
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Intel Apollo Lake SoC exposes serial SPI flash through the LPC device. The
SPI flash host controller is not discoverable through PCI config cycles
because P2SB (function 0 of the device 13) is hidden by the BIOS. We unhide
the device briefly in order to read BAR 0 of the SPI host controller.
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: NLee Jones <lee.jones@linaro.org>
Acked-by: NMarek Vasut <marek.vasut@gmail.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Many Intel CPUs including Haswell, Broadwell and Baytrail have SPI serial
flash host controller as part of the LPC device. This will populate an MFD
cell suitable for the SPI host controller driver if we know that the LPC
device has one.
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

The Intel 8-series and 9-series PCH devices, described by the descriptors
LPC_LPT and LPC_9S although codenamed 'lynxpoint' do not use the same GPIO
register layout which is used by the gpio-lynxpoint driver.  They use the
same ICH_V5_GPIO layout as the gpio-ich driver.

See:
http://www.intel.com/content/www/us/en/chipsets/8-series-chipset-pch-datasheet.html
http://www.intel.com/content/www/us/en/chipsets/9-series-chipset-pch-datasheet.html

The devices described by "Mobile 4th Generation Intel Core Processor
Family I/O" manual use the gpio-lynxpoint driver and are described by the
LPC_LPT_LP descriptor.

See:
http://www.intel.com/content/www/us/en/processors/core/4th-gen-core-family-mobile-i-o-datasheet.htmlSigned-off-by: NDan Gora <dg@adax.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

ACPI WDAT table is the preferred way to use hardware watchdog over the
native iTCO_wdt. Windows only uses this table for its hardware watchdog
implementation so we should be relatively safe to trust it has been
validated by OEMs

Prevent iTCO watchdog creation if we detect that there is ACPI WDAT table.
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: NGuenter Roeck <linux@roeck-us.net>
Acked-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>

Adding Intel codename Lewisburg platform device IDs for PCH.
Signed-off-by: NAlexandra Yates <alexandra.yates@linux.intel.com>
Reviewed-by: NAndy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

The lpc_ich_cells array gives the wrong impression about the
relationship between the watchdog and GPIO devices. They are
completely distinct devices, so this patch separates the
array into distinct mfd_cell structs per device.

A side effect of removing the array, is that the lpc_cells enum
is no longer needed.
Signed-off-by: NAaron Sierra <asierra@xes-inc.com>
Acked-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Intel Sunrisepoint (Skylake PCH) has the iTCO watchdog accessible across
the SMBus, unlike previous generations of PCH/ICH where it was on the
LPC bus. Because it's on the SMBus, it doesn't make sense to pass around
a 'struct lpc_ich_info', and leaking the type of bus into the iTCO
watchdog driver is kind of backwards anyway.

This change introduces a new 'struct itco_wdt_platform_data' for use
inside the iTCO watchdog driver and by the upcoming Intel Sunrisepoint
code, which neatly avoids having to include lpc_ich headers in the i801
i2c driver.

This change is overdue because lpc_ich_info has already found its way
into other TCO watchdog users, notably the intel_pmc_ipc driver where
the watchdog actually isn't on the LPC bus as far as I can see.

A simple translation layer is provided for converting from the existing
'struct lpc_ich_info' inside the lpc_ich mfd driver.
Signed-off-by: NMatt Fleming <matt.fleming@intel.com>
Acked-by: Darren Hart <dvhart@linux.intel.com> [drivers/x86 refactoring]
Reviewed-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Using -1 as platform device id means that the platform driver core will not
assign any id to the device (the device name will not have id at all). This
results problems on systems that have multiple PCHs (Platform Controller
HUBs) because all of them also include their own copy of LPC device.

All the subsequent device creations will fail because there already exists
platform device with the same name.

Fix this by passing PLATFORM_DEVID_AUTO as platform device id. This makes
the platform device core to allocate new ids automatically.
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

The patch sorts IDs in the table for easier maintenance. There is no
functional change.
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

This patch just sorts IDs in the table for better maintenance. There is no
functional change.
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

This patch adds the LPC Device IDs for the Intel 9 Series PCH.
Signed-off-by: NJames Ralston <james.d.ralston@intel.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

This is the same as used in Baytrail so add the new PCI ID to the driver's
list of supported IDs.
Signed-off-by: NAlan Cox <alan@linux.intel.com>
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Panther Point PCH GPIO configuration is similar to V5 PCHs.
Signed-off-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

This patch adds the LPC Controller Device IDs for Watchdog and GPIO for
the Intel Bay Trail Atom SoC.
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
Reviewed-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

The NM10's GPIO is compatible with ICH v7 GPIO.
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
Tested-by: NDan Weinlader <danw@vs-networks.com>
Reviewed-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

The register layout of the Avoton is compatible with the iTCO v3
register layout.
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
Tested-by: NRajat Jain <rajatjain@juniper.net>
Reviewed-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Some newer Atom CPUs, eg Avoton and Bay Trail, use slightly different
register layouts for the iTCO than the current v1 and v2 iTCO.
Differences from previous iTCO versions include:
- The ACPI space is enabled in the "ACPI base address" register instead
  of the "ACPI control register"

- The "no reboot" functionality is set in the "Power Management
  Configuration" register instead of the "General Control and Status"
  (GCS) register or PCI configuration space.

- The "ACPI Control Register" is not present on v3.  The "Power
  Management Configuration Base Address" register resides at the same
  address is Avoton/Bay Trail.

To differentiate these newer chipsets create a new v3 iTCO version and
update the MFD driver to support them.
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
Tested-by: NRajat Jain <rajatjain@juniper.net>
Reviewed-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Future chipsets will use different register layouts that don't map
cleanly to the lpc_ich_cfg fields.  Remove the lpc_ich_cfg struct and
add explicit fields to the higher level lpc_ich_priv structure.

This change should have no functional impact.
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
Tested-by: NRajat Jain <rajatjain@juniper.net>
Reviewed-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Some chipsets don't currently have GPIO support enabled.  For these
chipsets don't go through the process of initializing the GPIO region.

Make the same change for the watchdog initialization for chipsets which
may not enable the WDT in the future.
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
Tested-by: NRajat Jain <rajatjain@juniper.net>
Reviewed-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

The original bitmask of 0x10 was incorrect and would result in a write
to a reserved read-only bit instead of enabling the ACPI I/O
region.  Update it to the proper value of 0x80.
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
Tested-by: NRajat Jain <rajatjain@juniper.net>
Reviewed-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Signed-off-by: NVincent Donnefort <vdonnefort@gmail.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

None of these files are actually using any __init type directives
and hence don't need to include <linux/init.h>.  Most are just a
left over from __devinit and __cpuinit removal, or simply due to
code getting copied from one driver to the next.
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Don't use DEFINE_PCI_DEVICE_TABLE macro, because this macro
is not preferred.
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Fix a copy paste error from the WPT support initial patch.
Signed-off-by: NJames Ralston <james.d.ralston@intel.com>
Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com>

This patch adds the TCO Watchdog Device IDs for the
Intel Wildcat Point-LP PCH.
Signed-off-by: NJames Ralston <james.d.ralston@intel.com>
Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com>

The driver core clears the driver data to NULL after device_release
or on probe failure. Thus, it is not needed to manually clear the
device driver data to NULL.
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

'lpc_chipset_info' is used only in this file.

Fix the following sparse warning:

drivers/mfd/lpc_ich.c:216:21: warning: symbol 'lpc_chipset_info' was not declared. Should it be static?
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

This patch adds the LPC Controller DeviceIDs for iTCO Watchdog for
the Intel Coleto Creek PCH.
Signed-off-by: NSeth Heasley <seth.heasley@intel.com>
Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com>

use module_pci_driver instead of init/exit, make code cleaner.
Signed-off-by: NLibo Chen <libo.chen@huawei.com>
Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com>

This patch adds the LPC Controller Device IDs for Watchdog and GPIO for
Intel Avoton SoC, to the lpc_ich driver.
Signed-off-by: NJames Ralston <james.d.ralston@intel.com>
Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com>

And fix a kzalloc argument inversion bug while converting to devres.
Signed-off-by: NAaron Sierra <asierra@xes-inc.com>
Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com>

This patch adds the Watchdog Timer Device IDs for the Intel Wellsburg PCH
Signed-off-by: NJames Ralston <james.d.ralston@intel.com>
Acked-by: NPeter Tyser <ptyser@xes-inc.com>
Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com>

In ICH5 and earlier the GPIOBASE and GPIOCTRL registers are found at
offsets 0x58 and 0x5C, respectively. This patch allows GPIO access to
properly be enabled (and disabled) for these chipsets.
Signed-off-by: NAgócs Pál <agocs.pal.86@gmail.com>
Signed-off-by: NAaron Sierra <asierra@xes-inc.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com>

CONFIG_HOTPLUG is going away as an option so __devexit is no
longer needed.
Signed-off-by: NBill Pemberton <wfp5p@virginia.edu>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Daniel Walker <dwalker@fifo99.com>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Acked-by: NDavid Brown <davidb@codeaurora.org>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>