1. 08 2月, 2007 10 次提交
    • S
      piix: fix 82371MX enablebits · d2872239
      Sergei Shtylyov 提交于
      According to the datasheet, Intel 82371MX (MPIIX) actually has only a
      single IDE channel mapped to the primary or secondary ports depending on
      the value of the bit 14 of the IDETIM register at PCI config.  offset 0x6C
      (the register at 0x6F which the driver refers to.  doesn't exist).  So,
      disguise the controller as dual channel and set enablebits masks/values
      such that only either primary or secondary channel is detected enabled. 
      Also, preclude the IDE probing code from reading PCI BARs, this controller
      just doesn't have them (it's not the separate PCI function like the other
      PCI controllers), it only decodes the legacy addresses.
      
      [ Alan sayeth " MPIIX does not work with or without the change.  It needs its
        own different driver and not to use setup-pci.  Huge job and since it works
        well with libata who cares.  Ditto the early PIIX chip." ]
      Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
      Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      d2872239
    • S
      hpt366: HPT36x PCI clock detection fix · 6273d26a
      Sergei Shtylyov 提交于
      Fix minor coding mistake in the HPT36x PCI clock detection code noticed by
      Bartlomiej Zolnierkiewicz -- it always reported 33 MHz due to the missing
      'break' statements.  This, however, most probably never mattered -- in fact, I
      was thinking of removing the 25/40 MHz cases completely since HPT36x BIOSes
      didn't seem to set any other value than 7 into the 'cmd_high_time' field, i.e.
       supported only 33 MHz PCI.
      
      Note that in the original driver there was another bug: 25 and 40 MHz cases
      were interchanged.  Since the 'cmd_high_time' field is in units of PCI clocks,
      a lower clock count just *cannot* correspond to a higher frequency, i.  e.  it
      should be 5 for 25 MHz PCI and 9 for 40 MHz PCI, not the other way around.
      Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
      Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      6273d26a
    • S
      hpt366: init code rewrite · 7b73ee05
      Sergei Shtylyov 提交于
      Finally, rework the driver init.  code to correctly handle all the chip
      variants HighPoint has created so far.  This should cure the rest of the
      timing issues in the driver (especially, on 66 MHz PCI) caused by the
      HighPoint's habit of switching the base DPLL clock with every new revision
      of the chips...
      
        - switch to using the enumeration type to differ between the numerous chip
          variants, matching PCI device/revision ID with the chip type early, at the
          init_setup stage;
      
        - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
          stop duplicating it for each channel by storing the pointer in the pci_dev
          structure: first, at the init_setup stage, point it to a static "template"
          with only the chip type and its specific base DPLL frequency, the highest
          supported DMA mode, and the chip settings table pointer filled, then, at
          the init_chipset stage, allocate per-chip instance  and fill it with the
          rest of the necessary information;
      
        - get rid of the constant thresholds in the HPT37x PCI clock detection code,
          switch  to calculating  PCI clock frequency based on the chip's base DPLL
          frequency;
      
        - switch to using the DPLL clock and enable UltraATA/133 mode by default on
          anything newer than HPT370/A;
      
        - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
          unify the HPT36x/37x setup code and the speedproc handlers by joining the
          register setting lists into the table indexed by the clock selected;
      
        - add enablebits for all the chips to avoid touching disabled channels
          (though the HighPoint BIOS seem to only disable the primary one on
          HPT371/N);
      
        - separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
          when setting an UltraDMA mode in hpt37x_tune_chipset().
      
      This version has been tested on HPT370/302/371N.
      
      Thanks to Alan for the inspiration. Hopefully, his libata driver will also
      benefit from the work done on this "obsolete" driver...
      Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
      Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      7b73ee05
    • S
      hpt366: clean up DMA timeout handling for HPT370 · 4bf63de2
      Sergei Shtylyov 提交于
      Clean up DMA timeout handling for HPT370:
      
      - hpt370_lostirq_timeout() cleared the DMA status which made __ide_dma_end()
         called afterwards return the incorrect result, and the DMA engine was reset
         both before and after stopping DMA while the HighPoint drivers only do it
         after (which seems logical) -- fix this and also rename the function;
      
      - get rid of the needless mutual recursion in hpt370_ide_dma_end() and
         hpt370_ide_dma_timeout();
      
      - get rid of hpt370_lostirq_timeout() since hwif->ide_dma_end() called from
         the driver's interrupt handler later does all its work.
      Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
      Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      4bf63de2
    • S
      hpt366: merge HPT37x speedproc handlers · 26ccb802
      Sergei Shtylyov 提交于
      Continue with the driver rewrite:
      
      - move the interrupt twiddling code from the speedproc handlers into the
          init_hwif_hpt366 which allows to merge the two HPT37x speedproc handlers
          into one;
      
      - get rid of in init_hpt366 which solely consists of the duplicate code, then
          fold init_hpt37x() into init_chipset_hpt366();
      
      - fix hpt3xx_tune_drive() to always set the PIO mode requested, not the best
          possible one, change hpt366_config_drive_xfer_rate() accordingly, simplify
          it a bit;
      
      - group all the DMA related code together init_hwif_hpt366(), and generally
          clean up and beautify it.
      Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
      Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      26ccb802
    • S
      hpt366: cache channel's MCR address · abc4ad4c
      Sergei Shtylyov 提交于
      Begin the real driver redesign. For the starters:
      
      - cache the offset of the IDE channel's MISC. control registers which are used
         throughout the driver in hwif->select_data;
      
      - only touch the relevant MCR when detecting the cable type on HPT374's
         function 1;
      
      - make HPT36x's speedproc handler look the same way as HPT37x ones; fix the
         PIO timing register mask for HPT37x.
      
      - rename all the HPT3xx register related variables consistently; clean up the
         whitespace.
      Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
      Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      abc4ad4c
    • S
      hpt366: switch to using pci_get_slot · b4586715
      Sergei Shtylyov 提交于
      Switch to using pci_get_slot() to get to the function 1 of HPT36x/374 chips --
      there's no need for the driver itself to walk the list of the PCI devices, and
      it also forgets to check the bus number of the device found.
      Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
      Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      b4586715
    • S
      hpt366: print the real chip name at startup · 90778574
      Sergei Shtylyov 提交于
      - Rework the driver setup code so that it prefixes the driver startup
        messages with the real chip name.
      
      - Print the measured f_CNT value and the DPLL setting for non-HPT3xx
        chips as well.
      
      - Claim the extra 240 bytes of I/O space for all chips, not only for
        those having PCI device ID of 0x0004.
      Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
      Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      90778574
    • A
      hpt366: rework rate filtering tidy · f36702b4
      Andrew Morton 提交于
      Cc: Sergei Shtylyov <sshtylyov@ru.mvista.com>
      Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      f36702b4
    • S
      hpt366: rework rate filtering · e139b0b0
      Sergei Shtylyov 提交于
      - Rework hpt3xx_ratemask() and hpt3xx_ratefilter() so that the former
        returns the max.  mode computed at the load time and doesn't have to do
        bad Ultra33 drive list lookups anymore; remove the duplicate code from
        the latter function.  Move the quirky drive list lookup into
        hpt3xx_quirkproc() where it should have been from the start...
      
      - Disable UltraATA/100 for HPT370 by default as the 33 MHz ATA clock
        being used does not allow for it, and this *greatly* increases the
        transfer speed.
      
      - Save some space by using byte-wide fields in struct hpt_info; switch to
        reading the 8-bit PCI revision ID reg.  only, not the whole 32-bit reg.
      
      - Start incrementing the driver version number with each patch (should
        have been done from the first one posted).
      Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
      Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      e139b0b0
  2. 07 2月, 2007 30 次提交