1. 01 11月, 2018 5 次提交
  2. 30 10月, 2018 1 次提交
    • R
      drm/i915: Prefer IS_GEN<n> check with bitmask. · 9e783375
      Rodrigo Vivi 提交于
      Whenever possible we should stick with IS_GEN<n> checks.
      
      Bitmaks has been introduced on commit ae7617f0 ("drm/i915:
      Allow optimized platform checks") for efficiency.
      
      Let's stick with it whenever possible.
      
      This patch was generated with coccinelle:
      
      spatch -sp_file is_gen.cocci *{c,h} --in-place
      
      is_gen.cocci:
      @gen2@ expression e; @@
      -INTEL_GEN(e) == 2
      +IS_GEN2(e)
      @gen3@ expression e; @@
      -INTEL_GEN(e) == 3
      +IS_GEN3(e)
      @gen4@ expression e; @@
      -INTEL_GEN(e) == 4
      +IS_GEN4(e)
      @gen5@ expression e; @@
      -INTEL_GEN(e) == 5
      +IS_GEN5(e)
      @gen6@ expression e; @@
      -INTEL_GEN(e) == 6
      +IS_GEN6(e)
      @gen7@ expression e; @@
      -INTEL_GEN(e) == 7
      +IS_GEN7(e)
      @gen8@ expression e; @@
      -INTEL_GEN(e) == 8
      +IS_GEN8(e)
      @gen9@ expression e; @@
      -INTEL_GEN(e) == 9
      +IS_GEN9(e)
      @gen10@ expression e; @@
      -INTEL_GEN(e) == 10
      +IS_GEN10(e)
      @gen11@ expression e; @@
      -INTEL_GEN(e) == 11
      +IS_GEN11(e)
      
      Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
      Signed-off-by: NRodrigo Vivi <rodrigo.vivi@intel.com>
      Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20181026195143.20353-1-rodrigo.vivi@intel.com
      9e783375
  3. 24 10月, 2018 2 次提交
  4. 23 10月, 2018 1 次提交
  5. 18 10月, 2018 1 次提交
  6. 17 10月, 2018 1 次提交
  7. 16 10月, 2018 1 次提交
  8. 15 10月, 2018 2 次提交
    • S
      drm/i915: Add YCBCR 4:2:0/4:4:4 support for LSPCON · 668b6c17
      Shashank Sharma 提交于
      LSPCON chips can generate YCBCR outputs, if asked nicely :).
      
      In order to generate YCBCR 4:2:0 outputs, a source must:
      - send YCBCR 4:4:4 signals to LSPCON
      - program color space as 4:2:0 in AVI infoframes
      
      Whereas for YCBCR 4:4:4 outputs, the source must:
      - send YCBCR 4:4:4 signals to LSPCON
      - program color space as 4:4:4 in AVI infoframes
      
      So for both 4:2:0 as well as 4:4:4 outputs, we are driving the
      pipe for YCBCR 4:4:4 output, but AVI infoframe's color space
      information indicates LSPCON FW to start scaling down from YCBCR
      4:4:4 and generate YCBCR 4:2:0 output. As the scaling is done by
      LSPCON device, we need not to reserve a scaler for 4:2:0 outputs.
      
      V2: rebase
      V3: Addressed review comments from Ville
          - add enum crtc_output_format instead of bool ycbcr420
          - use crtc_output_format=4:4:4 for modeset of LSPCON 4:2:0 output
            cases in this way we will have YCBCR 4:4:4 framework ready (except
            the ABI part)
      V4: Added r-b from Maarten (for v3)
          Addressed review comments from Ville:
          - Do not add a non-atomic state variable to determine lspcon output.
            Instead add bool in CRTC state to indicate lspcon based scaling.
      V5: Addressed review comments from Ville:
          - Change the state bool name from external scaling to something more
            relavent.
          - Keep the info and adjusted_mode structures const.
          - use crtc_state instead of pipe_config.
          - Push all the config change into lspcon_ycbcr420_config function.
      V6: Rebase, small changes to accommodate changes in patch 2.
      V7: Fixed checkpatch warnings for alignment
      V8: Rebase
      
          PS: Ignored following warnings to match the current formatting:
          drm/i915: Add YCBCR 4:2:0/4:4:4 support for LSPCON
           -:53: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
          #53: FILE: drivers/gpu/drm/i915/i915_reg.h:8721:
          +#define  TRANS_MSA_SAMPLING_444        (2<<1)
                                                ^
          -:54: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
          #54: FILE: drivers/gpu/drm/i915/i915_reg.h:8722:
          +#define  TRANS_MSA_CLRSP_YCBCR         (2<<3)
      V9: Rebase
      V10: Rebase
      V11: Rebase
      
      Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
      Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
      Reviewed-by: NMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
      Signed-off-by: NShashank Sharma <shashank.sharma@intel.com>
      Signed-off-by: NJani Nikula <jani.nikula@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/1539325394-20788-8-git-send-email-shashank.sharma@intel.com
      668b6c17
    • S
      drm/i915: Introduce CRTC output format · d9facae6
      Shashank Sharma 提交于
      This patch adds an enum "intel_output_format" to represent
      the output format of a particular CRTC. This enum will be
      used to produce a RGB/YCBCR4:4:4/YCBCR4:2:0 output format
      during the atomic modeset calculations.
      
      V5:
      - Created this separate patch to introduce and init output_format.
      - Initialize parameters of output_format_str respectively (Jani N).
      - Call it intel_output_format than crtc_output_format(Ville).
      - Set output format in pipe_config for every encoder (Ville).
      - Get rid of extra DRM_DEBUG_KMS during get_pipe_config (Ville)
      
      V6: Rebase
      V7: Fixed alignment warnings (checkpatch)
      V8: Another check[atch warning for alignment
      V9: Rebase
      V10: Rebase on top of DSI restructure
      V11: Addressed review comment from Ville
      	- Set CRTC format for pre-HSW get_pipe_config() function too.
           Added Ville's R-B
      
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: NShashank Sharma <shashank.sharma@intel.com>
      Signed-off-by: NJani Nikula <jani.nikula@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/1539325394-20788-1-git-send-email-shashank.sharma@intel.com
      d9facae6
  9. 10 10月, 2018 2 次提交
  10. 09 10月, 2018 1 次提交
  11. 05 10月, 2018 2 次提交
  12. 28 9月, 2018 7 次提交
  13. 27 9月, 2018 1 次提交
  14. 19 9月, 2018 1 次提交
  15. 28 8月, 2018 1 次提交
  16. 26 8月, 2018 1 次提交
  17. 25 8月, 2018 1 次提交
    • P
      drm/i915/icl: implement the tc/legacy HPD {dis,}connect flows · 39d1e234
      Paulo Zanoni 提交于
      Unlike the other ports, TC ports are not available to use as soon as
      we get a hotplug. The TC PHYs can be shared between multiple
      controllers: display, USB, etc. As a result, handshaking through FIA
      is required around connect and disconnect to cleanly transfer
      ownership with the controller and set the type-C power state.
      
      This patch implements the flow sequences described by our
      specification. We opt to grab ownership of the ports as soon as we get
      the hotplugs in order to simplify the interactions and avoid surprises
      in the user space side. We may consider changing this in the future,
      once we improve our testing capabilities on this area.
      
      v2:
       * This unifies the DP and HDMI patches so we can discuss everything
         at once so people looking at random single patches can actually
         understand the direction.
       * I found out the spec was updated a while ago. There's a small
         difference in the connect flow and the patch was updated for that.
       * Our spec also now gives a good explanation on what is really
         happening. As a result, comments were added.
       * Add some more comments as requested by Rodrigo (Rodrigo).
      v3:
       * Downgrade a DRM_ERROR that shouldn't ever happen but we can't act
         on in case it does (Chris).
      
      BSpec: 21750, 4250.
      Cc: Animesh Manna <animesh.manna@intel.com>
      Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
      Reviewed-by: NRodrigo Vivi <rodrigo.vivi@intel.com>
      Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20180801173441.9789-1-paulo.r.zanoni@intel.com
      39d1e234
  18. 28 7月, 2018 1 次提交
  19. 26 7月, 2018 6 次提交
  20. 19 7月, 2018 2 次提交