Now that we advertise a PCIe capability, the Linux PCI layer will not scan
the bus for devices other than in slot 0.  This makes the work-around to
trap accesses to devices other than slot 0 unnecessary.

Tested-by: Willy Tarreau <w@1wt.eu> (Iomega iConnect Kirkwood, MiraBox Armada 370)
Tested-by: Andrew Lunn <andrew@lunn.ch> (D-Link DIR664 Kirkwood)
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> (Armada XP GP)
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>

Add a PCI Express root complex capability block so the PCI layer identifies
the bridge as a PCI Express device.

We expose this as a version 1 PCIe capability block, with slot support.  We
disable the clock power management capability as this depends on boards
wiring the CLKREQ# signal.

Tested-by: Willy Tarreau <w@1wt.eu> (Iomega iConnect Kirkwood, MiraBox Armada 370)
Tested-by: Andrew Lunn <andrew@lunn.ch> (D-Link DIR664 Kirkwood)
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> (Armada XP GP)
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>

Add an implementation to handle clock and reset handling that is compliant
with the PCIe specification.  The clock should be running and stable for
100us prior to reset being released, and we should re-assert reset prior to
stopping the clock.

Tested-by: Willy Tarreau <w@1wt.eu> (Iomega iConnect Kirkwood, MiraBox Armada 370)
Tested-by: Andrew Lunn <andrew@lunn.ch> (D-Link DIR664 Kirkwood)
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> (Armada XP GP)
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>

Use a gpio_desc to carry around the gpio, so we can then make use of the
GPIOF_ACTIVE_LOW property rather than carrying that around as well.  This
also avoids needing to use gpio_is_valid() to check whether we have a GPIO;
checking for a non-NULL descriptor is simpler.

Tested-by: Willy Tarreau <w@1wt.eu> (Iomega iConnect Kirkwood, MiraBox Armada 370)
Tested-by: Andrew Lunn <andrew@lunn.ch> (D-Link DIR664 Kirkwood)
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> (Armada XP GP)
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>

Rather than using devm_kzalloc() and multiplying the element and number,
use the provided devm_kcalloc() helper for this.

Tested-by: Willy Tarreau <w@1wt.eu> (Iomega iConnect Kirkwood, MiraBox Armada 370)
Tested-by: Andrew Lunn <andrew@lunn.ch> (D-Link DIR664 Kirkwood)
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> (Armada XP GP)
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>

We are in a context where we can sleep, and the PCIe reset gpio may be on
an I2C expander.  Use the cansleep() variant when setting the GPIO value.

Tested-by: Willy Tarreau <w@1wt.eu> (Iomega iConnect Kirkwood, MiraBox Armada 370)
Tested-by: Andrew Lunn <andrew@lunn.ch> (D-Link DIR664 Kirkwood)
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> (Armada XP GP)
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>

Split the PCIe port DT parsing and resource claiming from setting up the
actual ports.  This allows us to gather all the resources first, before
touching the hardware.  This is important as some of these resources (such
as the GPIO for the PCIe reset) may defer probing.

Tested-by: Willy Tarreau <w@1wt.eu> (Iomega iConnect Kirkwood, MiraBox Armada 370)
Tested-by: Andrew Lunn <andrew@lunn.ch> (D-Link DIR664 Kirkwood)
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> (Armada XP GP)
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>

The mvebu PCI port parsing is weak due to:

1) allocations via kasprintf() were not cleaned up when we encounter an
   error or decide to skip the port.
2) kasprintf() wasn't checked for failure.
3) of_get_named_gpio_flags() returns EPROBE_DEFER if the GPIO is not
   present, not devm_gpio_request_one().
4) the of_node was not being put when terminating the loop.

Fix these oversights.

Tested-by: Willy Tarreau <w@1wt.eu> (Iomega iConnect Kirkwood, MiraBox Armada 370)
Tested-by: Andrew Lunn <andrew@lunn.ch> (D-Link DIR664 Kirkwood)
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> (Armada XP GP)
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>

Move the PCIe port parsing and resource claiming to a separate function in
preparation to add proper cleanup of claimed resources.

Tested-by: Willy Tarreau <w@1wt.eu> (Iomega iConnect Kirkwood, MiraBox Armada 370)
Tested-by: Andrew Lunn <andrew@lunn.ch> (D-Link DIR664 Kirkwood)
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> (Armada XP GP)
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>

Use the port->name string which we previously formatted when referring to
the name of a port, rather than manually creating the port name each time.

Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> (Armada XP GP)
Tested-by: Andrew Lunn <andrew@lunn.ch> (Kirkwood DIR665)
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>

If we have a missing required property, report the full node name rather
than a vague "PCIe DT node" statement.  This allows the exact node in error
to be identified immediately.

Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> (Armada XP GP)
Tested-by: Andrew Lunn <andrew@lunn.ch> (Kirkwood DIR665)
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>

Rather than using for_each_child_of_node() and testing each child's
availability, use the for_each_available_child_of_node() helper instead.

Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> (Armada XP GP)
Tested-by: Andrew Lunn <andrew@lunn.ch> (Kirkwood DIR665)
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>

Rather than open-coding of_get_available_child_count(), use the provided
helper instead.

Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> (Armada XP GP)
Tested-by: Andrew Lunn <andrew@lunn.ch> (Kirkwood DIR665)
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>

The idea that you can arbitarily read 32-bits from PCI configuration space,
modify a sub-field (like the command register) and write it back without
consequence is deeply flawed.

Status registers (such as the status register, PCIe device status register,
etc) contain status bits which are read, write-one-to-clear.

What this means is that reading 32-bits from the command register,
modifying the command register, and then writing it back has the effect of
clearing any status bits that were indicating at that time.  Same for the
PCIe device control register clearing bits in the PCIe device status
register.

Since the Armada chips support byte, 16-bit and 32-bit accesses to the
registers (unless otherwise stated) and the PCI configuration data register
does not specify otherwise, it seems logical that the chip can indeed
generate the proper configuration access cycles down to byte level.

Testing with an ASM1062 PCIe to SATA mini-PCIe card on Armada 388.  PCIe
capability at 0x80, DevCtl at 0x88, DevSta at 0x8a.

Before:
  /# setpci -s 1:0.0 0x88.l		- DevSta: CorrErr+
  00012810
  /# setpci -s 1:0.0 0x88.w=0x2810	- Write DevCtl only
  /# setpci -s 1:0.0 0x88.l		- CorrErr cleared - FAIL
  00002810

After:
  /# setpci -s 1:0.0 0x88.l		- DevSta: CorrErr+
  00012810
  /# setpci -s 1:0.0 0x88.w=0x2810	- check DevCtl only write
  /# setpci -s 1:0.0 0x88.l		- CorErr remains set
  00012810
  /# setpci -s 1:0.0 0x88.w=0x281f	- check DevCtl write works
  /# setpci -s 1:0.0 0x88.l		- devctl field updated
  0001281f
  /# setpci -s 1:0.0 0x8a.w=0xffff	- clear DevSta
  /# setpci -s 1:0.0 0x88.l		- CorrErr now cleared
  0000281f
  /# setpci -s 1:0.0 0x88.w=0x2810	- restore DevCtl
  /# setpci -s 1:0.0 0x88.l		- check
  00002810

[bhelgaas: changelog]
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> (Armada XP GP)
Tested-by: Andrew Lunn <andrew@lunn.ch> (Kirkwood DIR665)
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>

PCI requires reads to reserved or unimplemented configuration space to
return zero and complete normally (see PCI r3.0, sec 6.1).  However, the
root port software implementation was returning 0xfffffff and
PCIBIOS_BAD_REGISTER_NUMBER.

Return zero when reading reserved or unimplemented config space.

[bhelgaas: changelog]
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> (Armada XP GP)
Tested-by: Andrew Lunn <andrew@lunn.ch> (Kirkwood DIR665)
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>

of_parse_phandle() returns a device_node pointer with the refcount
incremented.  We should dispose of this reference when we're finished.

Drop the reference acquired by of_parse_phandle().
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>

ARM previously stored the msi_controller pointer in its sysdata, struct
pci_sys_data, and implemented pcibios_msi_controller() to retrieve it.
That made PCI host controller drivers specific to ARM because they had to
put the msi_controller pointer in the ARM-specific pci_sys_data.

There is now a generic mechanism, pci_scan_root_bus_msi(), for giving the
msi_controller pointer to the PCI core.  Use this for all ARM systems and
for the DesignWare and Xilinx PCI host controller drivers.

This removes an ARM dependency from the DesignWare, DRA7xx, EXYNOS, i.MX6,
Keystone, Layerscape, SPEAr13xx, and Xilinx drivers.

[bhelgaas: changelog, split into separate patch]
Suggested-by: NRussell King <linux@arm.linux.org.uk>
Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NJingoo Han <jingoohan1@gmail.com>
CC: Pratyush Anand <pratyush.anand@gmail.com>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Simon Horman <horms@verge.net.au>
CC: Russell King <linux@arm.linux.org.uk>
CC: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
CC: Thierry Reding <thierry.reding@gmail.com>
CC: Michal Simek <michal.simek@xilinx.com>
CC: Marc Zyngier <marc.zyngier@arm.com>

Make pci-host-generic driver (kernel option PCI_HOST_GENERIC) available on
arm64.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

The generic OF-based host controller driver uses pci_common_init_dev(),
which is ARM-specific and requires the ARM struct hw_pci.  The part of
pci_common_init_dev() that is needed is limited and can be done here
without using hw_pci.

Note that the ARM pcibios functions expect the PCI sysdata to be a pointer
to a struct pci_sys_data.  Add a struct pci_sys_data as the first element
in struct gen_pci so that when we use a gen_pci pointer as sysdata, it is
also a pointer to a struct pci_sys_data.

Create and scan the root bus directly without using the ARM
pci_common_init_dev() interface.

[bhelgaas: changelog, move pcie_bus_configure_settings() before
pci_bus_add_devices(), combine !PCI_PROBE_ONLY blocks]
Tested-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Tested-by: NSuravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
Tested-by: NPavel Fedin <p.fedin@samsung.com>
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>

Simplify a trivial if-return sequence by combining it with a preceding
function call.

The semantic patch that makes this change is available in
scripts/coccinelle/misc/simple_return.cocci.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
CC: Lucas Stach <l.stach@pengutronix.de>

Use BUG_ON() instead of an if condition followed by BUG().

The semantic patch that makes this change is available in
scripts/coccinelle/misc/bugon.cocci.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
CC: Pratyush Anand <pratyush.anand@gmail.com>

There is no need to use the IS_ERR_VALUE() macro for checking the return
value from pm_runtime_* functions.

Test for a negative pm_runtime_get_sync() return value instead of using
IS_ERR_VALUE().

The semantic patch that makes this change is available in
scripts/coccinelle/api/pm_runtime.cocci.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
CC: Kishon Vijay Abraham I <kishon@ti.com>

There's a typo in commit e39758e0 in linux-next, which incorrectly
spells "msi_desc_to_pci_sysdata()" as "msi_desc_to_pci_sys_data()" and
causes build failure:

> ../drivers/pci/host/pcie-xilinx.c:235:3: error: implicit declaration
    of function 'msi_desc_to_pci_sys_data' [-Werror=implicit-function-declaration]

Fixes: e39758e0 "PCI: Use helper functions to access fields in struct msi_desc"
Signed-off-by: NJiang Liu <jiang.liu@linux.intel.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Mark Brown <broonie@kernel.org>
Cc: Stephen Rothwell <sfr@canb.auug.org.au>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Sören Brinkmann <soren.brinkmann@xilinx.com>
Cc: Srikanth Thokala <sthokal@xilinx.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Yijing Wang <wangyijing@huawei.com>
Link: http://lkml.kernel.org/r/1439912763-10645-1-git-send-email-jiang.liu@linux.intel.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

The PERST# line in am57x-evm is connected to a GPIO line and PERST# should
be driven high to indicate the clocks are stable (As per Figure 2-10: Power
Up of the PCIe CEM spec 3.0).

Add support to make GPIO drive PERST# line.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

DRA7xx requires the MSE bit to be cleared to set the master in standby
mode.  (In DRA7xx TRM_vE, section 24.9.4.5.2.2.1 PCIe Controller Master
Standby Behavior advises to use the clearing of the local MSE bit to set
the master in standby.  Without this some of the clocks do not idle).

Clear the MSE bit on suspend and enable it on resume.  Clearing MSE bit is
required to get clocks to be idled after suspend.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NJingoo Han <jingoohan1@gmail.com>

Add PM support to pci-dra7xx so PCI clocks can be disabled during suspend
and enabled during resume without affecting PCI functionality.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NJingoo Han <jingoohan1@gmail.com>

Fix the error handling when pm_runtime_get_sync() fails.

If pm_runtime_get_sync() fails, call pm_runtime_disable() so there are no
unbalanced pm_runtime_enable() calls.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NJingoo Han <jingoohan1@gmail.com>

Change CONFIG_PCIE_IPROC_BCMA to tristate to make it possible to build this
driver as a module.
Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NRay Jui <rjui@broadcom.com>

set_irq_flags is ARM-specific with custom flags which have genirq
equivalents.  Convert drivers to use the genirq interfaces directly, so we
can kill off set_irq_flags.  The translation of flags is as follows:

  IRQF_VALID -> !IRQ_NOREQUEST
  IRQF_PROBE -> !IRQ_NOPROBE
  IRQF_NOAUTOEN -> IRQ_NOAUTOEN

For IRQs managed by an irqdomain, the irqdomain core code handles clearing
and setting IRQ_NOREQUEST already, so there is no need to do this in .map()
functions, and we can simply remove the set_irq_flags calls.  Some users
also modify IRQ_NOPROBE, and this has been maintained although it is not
clear that is really needed.  There appears to be a great deal of blind
copy and paste of this code.
Signed-off-by: NRob Herring <robh@kernel.org>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NJingoo Han <jingoohan1@gmail.com>
CC: Kishon Vijay Abraham I <kishon@ti.com>
CC: Murali Karicheri <m-karicheri2@ti.com>
CC: Thierry Reding <thierry.reding@gmail.com>
CC: Stephen Warren <swarren@wwwdotorg.org>
CC: Alexandre Courbot <gnurou@gmail.com>
CC: Jingoo Han <jingoohan1@gmail.com>
CC: Pratyush Anand <pratyush.anand@gmail.com>
CC: Simon Horman <horms@verge.net.au>
CC: Michal Simek <michal.simek@xilinx.com>
CC: "Sören Brinkmann" <soren.brinkmann@xilinx.com>

Chained irq handlers usually set up handler data as well. We now have
a function to set both under irq_desc->lock. Replace the two calls
with one.
    
Search and conversion was done with coccinelle.
Reported-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Cc: Julia Lawall <Julia.Lawall@lip6.fr>
Cc: Duc Dang <dhdang@apm.com>

The X-Gene MSI driver only uses the msi_controller structure as
a way to match the host bridge  with its MSI HW, and thus the
msi_domain.

But now that we can directly associate an msi_domain with a device,
there is no use keeping this msi_controller around.

Just remove all traces of msi_controller from the driver.
Tested-by: NDuc Dang <dhdang@apm.com>
Acked-by: NBjorn Helgaas <bhelgaas@google.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Cc: <linux-arm-kernel@lists.infradead.org>
Cc: Yijing Wang <wangyijing@huawei.com>
Cc: Ma Jun <majun258@huawei.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Hanjun Guo <hanjun.guo@linaro.org>
Cc: Jiang Liu <jiang.liu@linux.intel.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Link: http://lkml.kernel.org/r/1438091186-10244-19-git-send-email-marc.zyngier@arm.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

The current iProc BCMA front-end driver can only work on ARM32 based
platforms; therefore its config option in Kconfig should be changed to
reflect that. This fixes arm64 allmodconfig build failure when compiling
the the iProc BCMA driver that contains struct pci_sys_data that is
arm32 specific
Signed-off-by: NRay Jui <rjui@broadcom.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Allow Broadcom iProc PCIe core driver to be compiled for ARM64
Signed-off-by: NRay Jui <rjui@broadcom.com>
Reviewed-by: NVikram Prakash <vikramp@broadcom.com>
Reviewed-by: NScott Branden <sbranden@broadcom.com>
Acked-by: NBjorn Helgaas <bhelgaas@google.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

PCI: iproc: Add arm64 support

Add arm64 support to the iProc PCIe driver.

Note that on arm32, bus->sysdata points to the arm32-specific
pci_sys_data struct, and pci_sys_data.private_data contains the
iproc_pcie pointer. For arm64, there's nothing corresponding to
pci_sys_data, so we keep the iproc_pcie pointer directly in
bus->sysdata.

In addition, arm64 does IRQ mapping in pcibios_add_device(), so it
doesn't need pci_fixup_irqs() as arm32 does.
Signed-off-by: NRay Jui <rjui@broadcom.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NScott Branden <sbranden@broadcom.com>
Acked-by: NBjorn Helgaas <bhelgaas@google.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Currently on Keystone SoCs, we always complain:

  keystone-pcie 21021000.pcie: missing *config* reg space

Keystone uses an older version of DesignWare hardware that doesn't have
ATU support.  So va_cfg0_base and va_cfg1_base are already set up in
ks_dw_pcie_host_init() before calling dw_pcie_host_init(), and they point
to the remote config space address va (both same for Keystone).  Add a
check to avoid this boot noise on Keystone.
Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Add arm64 support to the iProc PCIe driver.

Note that on arm32, bus->sysdata points to the arm32-specific pci_sys_data
struct, and pci_sys_data.private_data contains the iproc_pcie pointer.
For arm64, there's nothing corresponding to pci_sys_data, so we keep the
iproc_pcie pointer directly in bus->sysdata.

In addition, arm64 does IRQ mapping in pcibios_add_device(), so it doesn't
need pci_fixup_irqs() as arm32 does.
Signed-off-by: NRay Jui <rjui@broadcom.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NScott Branden <sbranden@broadcom.com>

Use helper functions to access fields in struct msi_desc, so we could
easily refine msi_desc later.
Signed-off-by: NJiang Liu <jiang.liu@linux.intel.com>
Reviewed-by: NYijing Wang <wangyijing@huawei.com>
Cc: Tony Luck <tony.luck@intel.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Stuart Yoder <stuart.yoder@freescale.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Pratyush Anand <pratyush.anand@gmail.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Soeren Brinkmann <soren.brinkmann@xilinx.com>
Cc: Srikanth Thokala <sthokal@xilinx.com>
Cc: Rob Herring <robh@kernel.org>
Link: http://lkml.kernel.org/r/1436428847-8886-9-git-send-email-jiang.liu@linux.intel.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

X-Gene PCIe controller has registers to support multiple memory ranges.

Add support for a 64-bit prefetchable memory window.

[bhelgaas: changelog]
Signed-off-by: NDuc Dang <dhdang@apm.com>
Signed-off-by: NTanmay Inamdar <tinamdar@apm.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Occasionally both MSI and INTx bits in the interrupt decode register are
set at once by the Xilinx AXI PCIe Bridge, so the MSI flag in the interrupt
message should be checked to ensure that the correct handler is used.

If this check is not in place and the interrupt message type is MSI, the
INTx handler will be used erroneously when both type bits are set.  This
will also be followed by a second read of the message FIFO, which can
result in the function returning early and the interrupt decode register
not being cleared if the FIFO is now empty.
Signed-off-by: NRussell Joyce <russell.joyce@york.ac.uk>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Signed-off-by: NThomas Gleixner <tglx@linutronix.de>