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  1. 21 4月, 2021 3 次提交
  3. 14 4月, 2021 2 次提交
    • L
      drm/i915/display: rename display version macros · 93e7e61e
      由 Lucas De Marchi 提交于 
      While converting the rest of the driver to use GRAPHICS_VER() and
MEDIA_VER(), following what was done for display, some discussions went
back on what we did for display:

	1) Why is the == comparison special that deserves a separate
	macro instead of just getting the version and comparing directly
	like is done for >, >=, <=?

	2) IS_DISPLAY_RANGE() is weird in that it omits the "_VER" for
	brevity. If we remove the current users of IS_DISPLAY_VER(), we
	could actually repurpose it for a range check

With (1) there could be an advantage if we used gen_mask since multiple
conditionals be combined by the compiler in a single and instruction and
check the result. However a) INTEL_GEN() doesn't use the mask since it
would make the code bigger everywhere else and b) in the cases it made
sense, it also made sense to convert to the _RANGE() variant.

So here we repurpose IS_DISPLAY_VER() to work with a [ from, to ] range
like was the IS_DISPLAY_RANGE() and convert the current IS_DISPLAY_VER()
users to use == and != operators. Aside from the definition changes,
this was done by the following semantic patch:

	@@ expression dev_priv, E1; @@
	- !IS_DISPLAY_VER(dev_priv, E1)
	+ DISPLAY_VER(dev_priv) != E1

	@@ expression dev_priv, E1; @@
	- IS_DISPLAY_VER(dev_priv, E1)
	+ DISPLAY_VER(dev_priv) == E1

	@@ expression dev_priv, from, until; @@
	- IS_DISPLAY_RANGE(dev_priv, from, until)
	+ IS_DISPLAY_VER(dev_priv, from, until)

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: NJani Nikula <jani.nikula@intel.com>
Signed-off-by: NLucas De Marchi <lucas.demarchi@intel.com>
[Jani: Minor conflict resolve while applying.]
Signed-off-by: NJani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20210413051002.92589-4-lucas.demarchi@intel.com
      93e7e61e
    • M
      drm/i915/display: Eliminate IS_GEN9_{BC,LP} · 2446e1d6
      由 Matt Roper 提交于 
      Now that we've eliminated INTEL_GEN(), IS_GEN_RANGE(), etc. from the
display code, we should also kill off our use of the IS_GEN9_* macros
too.  We'll do the conversion manually this time instead of using
Coccinelle since the most logical substitution can depend heavily on the
code context, and sometimes we can keep the code simpler if we make
additional adjustments such as swapping the order of if/else arms.

v2:
 - Restore a lost negation in intel_pll_is_valid().

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: NMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: NRadhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210407203945.1432531-1-matthew.d.roper@intel.com
(cherry picked from commit 70bfb307)
[Jani: cherry picked to topic branch to reduce conflicts]
Signed-off-by: NJani Nikula <jani.nikula@intel.com>
      2446e1d6
  5. 10 4月, 2021 2 次提交
  7. 08 4月, 2021 1 次提交
  9. 29 3月, 2021 1 次提交
  11. 24 3月, 2021 2 次提交
    • M
      drm/i915/display: Simplify GLK display version tests · 2b5a4562
      由 Matt Roper 提交于 
      GLK has always been a bit of a special case since it reports INTEL_GEN()
as 9, but has version 10 display IP.  Now we can properly represent the
display version as 10 and simplify the display generation tests
throughout the display code.

Aside from manually adding the version to the glk_info structure, the
rest of this patch is generated with a Coccinelle semantic patch.  Note
that we also need to switch any code that matches gen10 today but *not*
GLK to be CNL-specific:

        @@ expression dev_priv; @@
        - DISPLAY_VER(dev_priv) > 9
        + DISPLAY_VER(dev_priv) >= 10

        @@ expression dev_priv, E; @@
        (
        - DISPLAY_VER(dev_priv) >= 10 && E
        + (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) && E
        |
        - DISPLAY_VER(dev_priv) >= 10
        + DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)
        |
        - IS_DISPLAY_RANGE(dev_priv, 10, E)
        + IS_DISPLAY_RANGE(dev_priv, 11, E) || IS_CANNONLAKE(dev_priv)
        )

        @@ expression dev_priv, E, E2; @@
        (
        - (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
        + IS_DISPLAY_VER(dev_priv, 10)
        |
        - E || IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)
        + E || IS_DISPLAY_VER(dev_priv, 10)
        |
        - (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
        + IS_DISPLAY_VER(dev_priv, 10)
        |
        - IS_GEMINILAKE(dev_priv) || E || IS_CANNONLAKE(dev_priv)
        + E || IS_DISPLAY_VER(dev_priv, 10)
        |
        - E || IS_GEMINILAKE(dev_priv) || E2 || IS_CANNONLAKE(dev_priv)
        + E || E2 || IS_DISPLAY_VER(dev_priv, 10)
        |
        - (IS_DISPLAY_VER(dev_priv, 10) || IS_GEMINILAKE(dev_priv))
        + IS_DISPLAY_VER(dev_priv, 10)
        |
        - (IS_GEMINILAKE(dev_priv) || IS_DISPLAY_VER(dev_priv, 10))
        + IS_DISPLAY_VER(dev_priv, 10)
        )

        @@ expression dev_priv; @@
        - (IS_DISPLAY_VER(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
        + IS_DISPLAY_VER(dev_priv, 9)

        @@ expression dev_priv; @@
        (
        - !(DISPLAY_VER(dev_priv) >= 11 || IS_DISPLAY_VER(dev_priv, 10))
        + DISPLAY_VER(dev_priv) < 10
        |
        - (DISPLAY_VER(dev_priv) >= 11 || IS_DISPLAY_VER(dev_priv, 10))
        + DISPLAY_VER(dev_priv) >= 10
        )

        @@ expression dev_priv, E; @@
        - E || DISPLAY_VER(dev_priv) >= 11 || IS_DISPLAY_VER(dev_priv, 10)
        + E || DISPLAY_VER(dev_priv) >= 10

        @@ expression dev_priv, E; @@
        - (IS_DISPLAY_RANGE(dev_priv, 11, E) || IS_DISPLAY_VER(dev_priv, 10))
        + IS_DISPLAY_RANGE(dev_priv, 10, E)

        @@ expression dev_priv; @@
        (
        - DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv) || IS_GEN9_LP(dev_priv)
        + DISPLAY_VER(dev_priv) >= 10 || IS_GEN9_LP(dev_priv)
        |
        - IS_GEN9_LP(dev_priv) || DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)
        + IS_GEN9_LP(dev_priv) || DISPLAY_VER(dev_priv) >= 10
        )

        @@ expression dev_priv, E; @@
        - !(DISPLAY_VER(dev_priv) >= E)
        + DISPLAY_VER(dev_priv) < E

v2:
 - Convert gen10 conditions that don't include GLK into CNL conditions.
   (Ville)

v3:
 - Rework coccinelle rules so that "ver>=10" turns into "ver>=11||is_cnl." (Ville)

v3.1:
 - Manually re-add the ".display.version = 10" to glk_info after
   regenerating patch via Coccinelle.

v4:
 - Also apply cocci rules to intel_pm.c and i915_irq.c!  (CI)

Cc: Ville Syrjälä <ville.syrjala@intel.com>
Signed-off-by: NMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210322233840.4056851-1-matthew.d.roper@intel.com
      2b5a4562
    • M
      drm/i915/display: Eliminate most usage of INTEL_GEN() · 005e9537
      由 Matt Roper 提交于 
      Use Coccinelle to convert most of the usage of INTEL_GEN() and IS_GEN()
in the display code to use DISPLAY_VER() comparisons instead.  The
following semantic patch was used:

        @@ expression dev_priv, E; @@
        - INTEL_GEN(dev_priv) == E
        + IS_DISPLAY_VER(dev_priv, E)

        @@ expression dev_priv; @@
        - INTEL_GEN(dev_priv)
        + DISPLAY_VER(dev_priv)

        @@ expression dev_priv; expression E; @@
        - IS_GEN(dev_priv, E)
        + IS_DISPLAY_VER(dev_priv, E)

        @@
        expression dev_priv;
        expression from, until;
        @@
        - IS_GEN_RANGE(dev_priv, from, until)
        + IS_DISPLAY_RANGE(dev_priv, from, until)

There are still some display-related uses of INTEL_GEN() in intel_pm.c
(watermark code) and i915_irq.c.  Those will be updated separately.

v2:
 - Use new IS_DISPLAY_RANGE and IS_DISPLAY_VER helpers.  (Jani)
Signed-off-by: NMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: NLucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210320044245.3920043-4-matthew.d.roper@intel.com
      005e9537
  13. 24 2月, 2021 1 次提交
  15. 10 2月, 2021 1 次提交
  17. 01 2月, 2021 2 次提交
  19. 21 1月, 2021 1 次提交
  21. 14 1月, 2021 2 次提交
  23. 03 12月, 2020 4 次提交
  25. 17 11月, 2020 1 次提交
    • B
      drm/i915: Tweaked Wa_14010685332 for PCHs used on gen11 platforms · b896898c
      由 Bob Paauwe 提交于 
      The WA specifies that we need to toggle a SDE chicken bit on and then
off as the final step in preparation for s0ix entry.

    Bspec: 33450
    Bspec: 8402

However, something is happening after we toggle the bit that causes
the WA to be invalidated. This makes dispcnlunit1_cp_xosc_clkreq
active being already in s0ix state i.e SLP_S0 counter incremented.
Tweaking the Wa_14010685332 by setting the bit on suspend and clearing
it on resume turns down the dispcnlunit1_cp_xosc_clkreq.
B.Spec has Documented this tweaked sequence of WA as an alternative.
Let keep this tweaked WA for Gen11 platforms and keep untweaked WA for
other platforms which never observed this issue.

v2 (MattR):
 - Change the comment on the workaround to give PCH names rather than
   platform names.  Although the bspec is setup to list workarounds by
   platform, the hardware team has confirmed that the actual issue being
   worked around here is something that was introduced back in the
   Cannon Lake PCH and carried forward to subsequent PCH's.
 - Extend the untweaked version of the workaround to include  PCH_CNP as
   well.  Note that since PCH_CNP is used to represent CMP, this will
   apply on CML and some variants of RKL too.
 - Cap the untweaked version of the workaround so that it won't apply to
   "fake" PCH's (i.e., DG1).  The issue we're working around really is
   an issue in the PCH itself, not the South Display, so it shouldn't
   apply when there isn't a real PCH.

v3:
 - use intel_de_rmw(). [Rodrigo]

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: NBob Paauwe <bob.j.paauwe@intel.com>
Signed-off-by: NAnshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: NMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201110121700.4338-1-anshuman.gupta@intel.comReviewed-by: NRodrigo Vivi <rodrigo.vivi@intel.com>
      b896898c
  27. 12 11月, 2020 2 次提交
  29. 21 10月, 2020 1 次提交
    • V
      drm/i915: Reorder hpd init vs. display resume · 4c8d4651
      由 Ville Syrjälä 提交于 
      Currently we call .hpd_irq_setup() directly just before display
resume, and follow it with another call via intel_hpd_init()
just afterwards. Assuming the hpd pins are marked as enabled
during the open-coded call these two things do exactly the
same thing (ie. enable HPD interrupts). Which even makes sense
since we definitely need working HPD interrupts for MST sideband
during the display resume.

So let's nuke the open-coded call and move the intel_hpd_init()
call earlier. However we need to leave the poll_init_work stuff
behind after the display resume as that will trigger display
detection while we're resuming. We don't want that trampling over
the display resume process. To make this a bit more symmetric
we turn this into a intel_hpd_poll_{enable,disable}() pair.
So we end up with the following transformation:
intel_hpd_poll_init() -> intel_hpd_poll_enable()
lone intel_hpd_init() -> intel_hpd_init()+intel_hpd_poll_disable()
.hpd_irq_setup()+resume+intel_hpd_init() -> intel_hpd_init()+resume+intel_hpd_poll_disable()

If we really would like to prevent all *long* HPD processing during
display resume we'd need some kind of software mechanism to simply
ignore all long HPDs. Currently we appear to have that just for
fbdev via ifbdev->hpd_suspended. Since we aren't exploding left and
right all the time I guess that's mostly sufficient.

For a bit of history on this, we first got a mechanism to block
hotplug processing during suspend in commit 15239099 ("drm/i915:
enable irqs earlier when resuming") on account of moving the irq enable
earlier. This then got removed in commit 50c3dc97 ("drm/fb-helper:
Fix hpd vs. initial config races") because the fdev initial config
got pushed to a later point. The second ad-hoc hpd_irq_setup() for
resume was added in commit 0e32b39c ("drm/i915: add DP 1.2 MST
support (v0.7)") to be able to do MST sideband during the resume.
And finally we got a partial resurrection of the hpd blocking
mechanism in commit e8a8fedd ("drm/i915: Block fbdev HPD
processing during suspend"), but this time it only prevent fbdev
from handling hpd while resuming.

v2: Leave the poll_init_work behind
v3: Remove the extra intel_hpd_poll_disable() from display reset (Lyude)
    Add the missing intel_hpd_poll_disable() to display init (Imre)

Cc: Lyude Paul <lyude@redhat.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201013181137.30560-1-ville.syrjala@linux.intel.comReviewed-by: NImre Deak <imre.deak@intel.com>
Reviewed-by: NLyude Paul <lyude@redhat.com>
      4c8d4651
  31. 20 10月, 2020 1 次提交
  33. 16 10月, 2020 5 次提交
  35. 29 8月, 2020 1 次提交
    • J
      drm/i915/tgl: Fix stepping WA matching · c33298cb
      由 José Roberto de Souza 提交于 
      TGL made stepping a litte mess, workarounds refer to the stepping of
the IP(GT or Display) not of the GPU stepping so it would already
require the same solution as used in commit 96c5a15f
("drm/i915/kbl: Fix revision ID checks").
But to make things even more messy it have a different IP stepping
mapping between SKUs and the same stepping revision of GT do not match
the same HW between TGL U/Y and regular TGL.

So it was required to have 2 different macros to check GT WAs while
for Display we are able to use just one macro that uses the right
revids table.

All TGL workarounds checked and updated accordingly.

v2:
- removed TODO to check if WA 14010919138 applies to regular TGL.
- fixed display stepping in regular TGL (Anusha)

BSpec: 52890
BSpec: 55378
BSpec: 44455
Reviewed-by: NAnusha Srivatsa <anusha.srivtsa@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Penne Lee <penne.y.lee@intel.com>
Cc: Guangyao Bai <guangyao.bai@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: NJosé Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200827233943.400946-1-jose.souza@intel.com
      c33298cb
  37. 19 8月, 2020 2 次提交
  39. 18 8月, 2020 4 次提交
  41. 03 7月, 2020 1 次提交