1. 05 1月, 2011 1 次提交
    • Y
      x86: Fix APIC ID sizing bug on larger systems, clean up MAX_APICS confusion · cb2ded37
      Yinghai Lu 提交于
      Found one x2apic pre-enabled system, x2apic_mode suddenly get
      corrupted after register some cpus, when compiled
      CONFIG_NR_CPUS=255 instead of 512.
      
      It turns out that generic_processor_info() ==> phyid_set(apicid,
      phys_cpu_present_map) causes the problem.
      
      phys_cpu_present_map is sized by MAX_APICS bits, and pre-enabled
      system some cpus have an apic id > 255.
      
      The variable after phys_cpu_present_map may get corrupted
      silently:
      
       ffffffff828e8420 B phys_cpu_present_map
       ffffffff828e8440 B apic_verbosity
       ffffffff828e8444 B local_apic_timer_c2_ok
       ffffffff828e8448 B disable_apic
       ffffffff828e844c B x2apic_mode
       ffffffff828e8450 B x2apic_disabled
       ffffffff828e8454 B num_processors
       ...
      
      Actually phys_cpu_present_map is referenced via apic id, instead
      index. We should use MAX_LOCAL_APIC instead MAX_APICS.
      
      For 64-bit it will be 32768 in all cases. BSS will increase by 4k bytes
      on 64-bit:
      
      	text		data		bss		dec		filename
      	21696943	4193748		12787712	38678403	vmlinux.before
      	21696943	4193748		12791808	38682499	vmlinux.after
      
      No change on 32bit.
      
      Finally we can remove MAX_APCIS that was rather confusing.
      Signed-off-by: NYinghai Lu <yinghai@kernel.org>
      Cc: H. Peter Anvin <hpa@linux.intel.com>
      Cc: "Eric W. Biederman" <ebiederm@xmission.com>
      LKML-Reference: <4D23BD9C.3070102@kernel.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      cb2ded37
  2. 04 1月, 2011 1 次提交
    • C
      x86, UV, BAU: Extend for more than 16 cpus per socket · cfa60917
      Cliff Wickman 提交于
      Fix a hard-coded limit of a maximum of 16 cpu's per socket.
      
      The UV Broadcast Assist Unit code initializes by scanning the
      cpu topology of the system and assigning a master cpu for each
      socket and UV hub. That scan had an assumption of a limit of 16
      cpus per socket. With Westmere we are going over that limit.
      The UV hub hardware will allow up to 32.
      
      If the scan finds the system has gone over that limit it returns
      an error and we print a warning and fall back to doing TLB
      shootdowns without the BAU.
      Signed-off-by: NCliff Wickman <cpw@sgi.com>
      Cc: <stable@kernel.org> # .37.x
      LKML-Reference: <E1PZol7-0000mM-77@eag09.americas.sgi.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      cfa60917
  3. 10 12月, 2010 2 次提交
  4. 07 12月, 2010 1 次提交
  5. 06 12月, 2010 1 次提交
    • D
      ce4100: Add errata fixes for UART on CE4100 · 5ec6960f
      Dirk Brandewie 提交于
      This patch enables the UART on the CE4100. The UART has a couple of
      issues that need to be worked around. First the UART is mostly PC
      compatible except that it is clocked eight times faster than a
      standard PC so the default configuration provided in
      arch/x86/include/asm/serial.h needs to be overridden. Second the TX
      interrupt may not be set correctly all the time. Lastly accessing the
      UART via I/O space for early_prink() hangs the chip when the IOAPIC is
      enabled.
      
      A custom mem_serial_in() is provided to work around the TX interrupt
      issue. The configuration issues are dealt with in the call back
      registered with the 8250 driver via serial8250_set_isa_configurator()
      Signed-off-by: NDirk Brandewie <dirk.brandewie@gmail.com>
      LKML-Reference: <1290436128-17958-1-git-send-email-dirk.brandewie@gmail.com>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      5ec6960f
  6. 20 11月, 2010 1 次提交
  7. 19 11月, 2010 1 次提交
  8. 18 11月, 2010 1 次提交
    • D
      x86: UV: Address interrupt/IO port operation conflict · 8191c9f6
      Dimitri Sivanich 提交于
      This patch for SGI UV systems addresses a problem whereby
      interrupt transactions being looped back from a local IOH,
      through the hub to a local CPU can (erroneously) conflict with
      IO port operations and other transactions.
      
      To workaound this we set a high bit in the APIC IDs used for
      interrupts. This bit appears to be ignored by the sockets, but
      it avoids the conflict in the hub.
      Signed-off-by: NDimitri Sivanich <sivanich@sgi.com>
      LKML-Reference: <20101116222352.GA8155@sgi.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      ___
      
       arch/x86/include/asm/uv/uv_hub.h   |    4 ++++
       arch/x86/include/asm/uv/uv_mmrs.h  |   19 ++++++++++++++++++-
       arch/x86/kernel/apic/x2apic_uv_x.c |   25 +++++++++++++++++++++++--
       arch/x86/platform/uv/tlb_uv.c      |    2 +-
       arch/x86/platform/uv/uv_time.c     |    4 +++-
       5 files changed, 49 insertions(+), 5 deletions(-)
      8191c9f6
  9. 12 11月, 2010 2 次提交
  10. 11 11月, 2010 4 次提交
  11. 10 11月, 2010 1 次提交
  12. 09 11月, 2010 2 次提交
    • J
      x86: mrst: Parse SFI timer table for all timer configs · 7f05dec3
      Jacob Pan 提交于
      Penwell has APB timer based watchdog timers, it requires platform code to parse
      SFI MTMR tables in order to claim its timer.
      
      This patch will always parse SFI MTMR regardless of system timer configuration
      choices. Otherwise, SFI MTMR table may not get parsed if running on Medfield
      with always-on local APIC timers and constant TSC. Watchdog timer driver will
      then not get a timer to use.
      Signed-off-by: NJacob Pan <jacob.jun.pan@linux.intel.com>
      Signed-off-by: NAlan Cox <alan@linux.intel.com>
      LKML-Reference: <20101109112800.20591.10802.stgit@localhost.localdomain>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      7f05dec3
    • F
      x86/mrst: Add SFI platform device parsing code · 1da4b1c6
      Feng Tang 提交于
      SFI provides a series of tables. These describe the platform devices present
      including SPI and I²C devices, as well as various sensors, keypads and other
      glue as well as interfaces provided via the SCU IPC mechanism (intel_scu_ipc.c)
      
      This patch is a merge of the core elements and relevant fixes from the
      Intel development code by Feng, Alek, myself into a single coherent patch
      for upstream submission.
      
      It provides the needed infrastructure to register I2C, SPI and platform devices
      described by the tables, as well as handlers for some of the hardware already
      supported in kernel. The 0.8 firmware also provides GPIO tables.
      
      Devices are created at boot time or if they are SCU dependant at the point an
      SCU is discovered. The existing Linux device mechanisms will then handle the
      device binding. At an abstract level this is an SFI to Linux device translator.
      
      Device/platform specific setup/glue is in this file. This is done so that the
      drivers for the generic I²C and SPI bus devices remain cross platform as they
      should.
      
      (Updated from RFC version to correct the emc1403 name used by the firmware
       and a wrongly used #define)
      Signed-off-by: NAlek Du <alek.du@linux.intel.com>
      LKML-Reference: <20101109112158.20013.6158.stgit@localhost.localdomain>
      [Clean ups, removal of 0.7 support]
      Signed-off-by: NFeng Tang <feng.tang@linux.intel.com>
      [Clean ups]
      Signed-off-by: NAlan Cox <alan@linux.intel.com>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      1da4b1c6
  13. 27 10月, 2010 8 次提交